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64 Commits

Author SHA1 Message Date
Evan Cheng aee7e49c50 PredCC is meant to be 2 bits wide, like PredCC1. 
llvm-svn: 78829
 2009-08-12 18:35:50 +00:00
Evan Cheng bb2af3555c Shrink Thumb2 movcc instructions. 
llvm-svn: 78790
 2009-08-12 05:17:19 +00:00
Evan Cheng 1e6c2a1c17 Shrink ADDS, ADC, RSB, and SUBS. 
llvm-svn: 78776
 2009-08-12 01:49:45 +00:00
Evan Cheng f6a9d06241 Shrinkify Thumb2 r = add sp, imm. 
llvm-svn: 78745
 2009-08-11 23:00:31 +00:00
Evan Cheng cc9ca3500d Shrinkify Thumb2 load / store multiple instructions. 
llvm-svn: 78717
 2009-08-11 21:11:32 +00:00
Evan Cheng 806845daec Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions. 
llvm-svn: 78659
 2009-08-11 09:37:40 +00:00
Evan Cheng 3606467709 Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to 
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.

llvm-svn: 78658
 2009-08-11 08:52:18 +00:00
Evan Cheng 5bb93ce769 Watch out for empty BB. 
llvm-svn: 78562
 2009-08-10 08:10:13 +00:00
Evan Cheng 8a640ae504 rev, rev16, and revsh do not set CPSR. 
llvm-svn: 78561
 2009-08-10 07:58:45 +00:00
Evan Cheng f16a1d5b79 Duh. Most 16-bit Thumb rr instructions are two-address. Fix table. 
llvm-svn: 78560
 2009-08-10 07:20:37 +00:00
Evan Cheng 1f5bee14a1 CPSR can be livein; transfer predicate operands correctly; tMUL is two-address. 
llvm-svn: 78559
 2009-08-10 06:57:42 +00:00
Evan Cheng 51cbd2d6c4 Add support to reduce most of 32-bit Thumb2 arithmetic instructions. 
llvm-svn: 78550
 2009-08-10 02:37:24 +00:00
Evan Cheng d461c1c559 Add support to convert 32-bit instructions to 16-bit non-two-address ones. 
llvm-svn: 78540
 2009-08-09 19:17:19 +00:00
Evan Cheng 1be453b462 Add a skeleton Thumb2 instruction size reduction pass. 
llvm-svn: 78456
 2009-08-08 03:21:23 +00:00