f0d25117c6
ARM VFP add encoding of the bitcount to fixed-point<-->floating point. insns.
...
The value from the operands isn't right yet, but we weren't encoding it at
all previously. The parser needs to twiddle the values when building the
instruction.
Partial for: rdar://10558523
llvm-svn: 147170
2011-12-22 19:55:21 +00:00
b65dd04923
Remove some bogus comments.
...
llvm-svn: 147169
2011-12-22 19:45:01 +00:00
489ed5929e
ARM pre-UAL aliases. fcmp[sd].
...
llvm-svn: 147158
2011-12-22 19:20:45 +00:00
12ccf45bbb
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
...
Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
21488b8839
ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
...
llvm-svn: 147152
2011-12-22 17:37:00 +00:00
3794d82af5
Tidy up. Trailing whitespace.
...
llvm-svn: 147151
2011-12-22 17:17:10 +00:00
62bffd8827
Nuke invalid comment from copy/paste.
...
llvm-svn: 147150
2011-12-22 17:04:50 +00:00
84d00f11cd
Make the virtual methods in ARMELFObjectWriter public.
...
llvm-svn: 147132
2011-12-22 02:58:12 +00:00
2da9777cef
Hopefully fix the cmake build.
...
llvm-svn: 147121
2011-12-22 01:11:01 +00:00
4449b21294
Fix name in comments.
...
llvm-svn: 147119
2011-12-22 01:06:53 +00:00
32a756b7ce
Unbreak cmake build after r147115.
...
llvm-svn: 147117
2011-12-22 01:03:35 +00:00
a0124055b1
Move the ARM specific parts of the ELF writer to Target/ARM.
...
llvm-svn: 147115
2011-12-22 00:37:50 +00:00
2b80dad572
ARM NEON mnemonic aliase for vrecpeq.
...
llvm-svn: 147109
2011-12-21 23:52:37 +00:00
7869d8c01e
ARM VFP optional data type on VMOV GPR<-->SPR.
...
llvm-svn: 147104
2011-12-21 23:24:15 +00:00
260b4b336a
ARM NEON optional data type on VSWP instructions.
...
llvm-svn: 147103
2011-12-21 23:09:28 +00:00
a50e24fcb3
ARM NEON mnemonic aliases for vzipq and vswpq.
...
llvm-svn: 147102
2011-12-21 23:04:33 +00:00
1152cc0cad
ARM asm parser should be more lenient w/ .thumb_func directive.
...
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
llvm-svn: 147100
2011-12-21 22:30:16 +00:00
8c59bbc1ed
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
...
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
b3ef713e44
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
...
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
3588a43e3a
Move common code into an MRI function.
...
llvm-svn: 147071
2011-12-21 19:50:05 +00:00
c80a264386
ARM NEON assmebly parsing for VLD2 to all lanes instructions.
...
llvm-svn: 147069
2011-12-21 19:40:55 +00:00
7248bda595
Fix a couple of copy-n-paste bugs. Noticed by George Russell!
...
llvm-svn: 147064
2011-12-21 18:56:22 +00:00
1ad4095d6b
Reduce the exposure of Triple::OSType in the ELF object writer. This will
...
avoid including ADT/Triple.h in many places when the target specific bits are
moved.
llvm-svn: 147059
2011-12-21 17:00:36 +00:00
dc8a1aaea6
Fix a couple of copy-n-paste bugs. Noticed by George Russell.
...
llvm-svn: 147032
2011-12-21 03:04:10 +00:00
7de7ab83fa
ARM assembly parsing allows constant expressions for lane indices.
...
llvm-svn: 147028
2011-12-21 01:19:23 +00:00
c5af54ec89
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
...
llvm-svn: 147025
2011-12-21 00:38:54 +00:00
cd22e4a81e
ARM .req register name aliases are case insensitive, just like regnames.
...
llvm-svn: 147009
2011-12-20 23:11:00 +00:00
4eda145c7f
Move comment to appropriate place.
...
llvm-svn: 147000
2011-12-20 22:26:38 +00:00
b95c102c2f
Heed spill slot alignment on ARM.
...
Use the spill slot alignment as well as the local variable alignment to
determine when the stack needs to be realigned. This works now that the
ARM target can always realign the stack by using a base pointer.
Still respect the ARMBaseRegisterInfo::canRealignStack() function
vetoing a realigned stack. Don't use aligned spill code in that case.
llvm-svn: 146997
2011-12-20 22:15:04 +00:00
2c59052984
ARM assembly parsing and encoding for VST2 single-element, double spaced.
...
llvm-svn: 146990
2011-12-20 20:46:29 +00:00
75e2ab5db2
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
...
llvm-svn: 146983
2011-12-20 19:21:26 +00:00
68132d8093
ARM target code clean up. Check for iOS, not Darwin where it makes sense.
...
llvm-svn: 146981
2011-12-20 18:26:50 +00:00
135d244b56
First steps in ARM AsmParser support for .eabi_attribute and .arch
...
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
llvm-svn: 146977
2011-12-20 17:38:12 +00:00
e805b16e3d
Fix up the CMake build for the new files added in r146960, they're
...
likely to stay either way that discussion ends up resolving itself.
llvm-svn: 146966
2011-12-20 08:42:11 +00:00
a379b18173
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
...
llvm-svn: 146960
2011-12-20 02:50:00 +00:00
75f12cc3fe
Mark ARM eh_sjlj_dispatchsetup as clobbering all registers. Radar 10567930.
...
We used to rely on the *eh_sjlj_setjmp instructions to mark that a function
with setjmp/longjmp exception handling clobbers all the registers. But with
the recent reorganization of ARM EH, those eh_sjlj_setjmp instructions are
expanded away earlier, before PEI can see them to determine what registers to
save and restore. Mark the dispatchsetup instruction in the same way, since
that instruction cannot be expanded early. This also more accurately reflects
when the registers are clobbered.
llvm-svn: 146949
2011-12-20 01:29:27 +00:00
e2ca9e5b5f
ARM assembly shifts by zero should be plain 'mov' instructions.
...
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
045b6c71a6
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
...
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"
rdar://10603913
llvm-svn: 146925
2011-12-19 23:51:07 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
64f4de29e0
ARM NEON two-operand aliases for VPADD.
...
rdar://10602276
llvm-svn: 146895
2011-12-19 19:51:03 +00:00
e16acacc3a
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
...
llvm-svn: 146892
2011-12-19 19:43:50 +00:00
92a939ae73
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
...
llvm-svn: 146887
2011-12-19 19:02:41 +00:00
9ae4fc035b
ARM NEON implied destination aliases for VMAX/VMIN.
...
llvm-svn: 146885
2011-12-19 18:57:38 +00:00
cef98cddbe
ARM NEON relax parse time diagnostics for alignment specifiers.
...
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
a7d2421603
Tidy up.
...
llvm-svn: 146882
2011-12-19 18:11:17 +00:00
24159e346d
Remove a register class that can just as well be synthesized.
...
Add the new TableGen register class synthesizer feature to the release
notes.
llvm-svn: 146875
2011-12-19 16:53:40 +00:00
c7b437ae34
Emit a getMatchingSuperRegClass() implementation for every target.
...
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().
Delete the old manual, error-prone implementations in the targets.
llvm-svn: 146873
2011-12-19 16:53:34 +00:00
903231bc58
Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.
...
llvm-svn: 146805
2011-12-17 01:25:34 +00:00
465cdf3ba4
Preserve more memory operands in ARMExpandPseudo.
...
I don't think this affects anything but verbose assembly.
llvm-svn: 146787
2011-12-17 00:07:02 +00:00
9790187b6c
Fix off-by-one error in bucket sort.
...
The bad sorting caused a misaligned basic block when building 176.vpr in
ARM mode.
<rdar://problem/10594653>
llvm-svn: 146767
2011-12-16 23:00:05 +00:00
Jim Grosbach