f4ebec03e0
putback r116983 and fix simple-fp-encoding.ll tests
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llvm-svn: 116992
2010-10-21 03:40:16 +00:00
9e00f27e14
Revert r116983, which is breaking all the buildbots.
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llvm-svn: 116987
2010-10-21 03:11:16 +00:00
15c2ac90ec
Add missing scheduling itineraries for transfers between core registers and VFP registers.
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llvm-svn: 116983
2010-10-21 01:12:00 +00:00
1958cefd69
Model operand cycles of vldm / vstm; also fixes scheduling itineraries of vldr / vstr, etc.
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llvm-svn: 115898
2010-10-07 01:50:48 +00:00
49d4c0bd18
- Add TargetInstrInfo::getOperandLatency() to compute operand latencies. This
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allow target to correctly compute latency for cases where static scheduling
itineraries isn't sufficient. e.g. variable_ops instructions such as
ARM::ldm.
This also allows target without scheduling itineraries to compute operand
latencies. e.g. X86 can return (approximated) latencies for high latency
instructions such as division.
- Compute operand latencies for those defined by load multiple instructions,
e.g. ldm and those used by store multiple instructions, e.g. stm.
llvm-svn: 115755
2010-10-06 06:27:31 +00:00
2fb20b1d37
ARM instruction itinerary fixes:
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1. Cortex-a9 8-bit and 16-bit loads / stores AGU cycles are 1 cycle longer than 32-bit ones.
2. Cortex-a9 is out-of-order so model all read cycles as cycle 1.
3. Lots of other random fixes for A8 and A9.
llvm-svn: 115121
2010-09-30 01:08:25 +00:00
2259d67a33
Separate itinerary classes for mvn from mov; for tst / teq from cmp / cmn.
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llvm-svn: 115010
2010-09-29 00:49:25 +00:00
c35d7bbe43
Assign bitwise binary instructions different itinerary classes from ALU instructions such as add / sub.
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llvm-svn: 115008
2010-09-29 00:27:46 +00:00
0097dd0d5a
Add support to model pipeline bypass / forwarding.
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llvm-svn: 115005
2010-09-28 23:50:49 +00:00
8f9a2244fc
Remove a unused instruction itinerary class.
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llvm-svn: 114782
2010-09-25 01:06:02 +00:00
62d626ce86
Fix zero and sign extension instructions scheduling itineraries.
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llvm-svn: 114780
2010-09-25 00:49:35 +00:00
e37da03e60
More pseudo instruction scheduling itinerary fixes.
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llvm-svn: 114768
2010-09-24 22:41:41 +00:00
367a5df8cf
For each instruction itinerary class, specify the number of micro-ops each
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instruction in the class would be decoded to. Or zero if the number of
uOPs must be determined dynamically.
This will be used to determine the cost-effectiveness of predicating a
micro-coded instruction.
llvm-svn: 113513
2010-09-09 18:18:55 +00:00
84511e1526
Clean up 80 column violations. No functional change.
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llvm-svn: 105350
2010-06-02 21:53:11 +00:00
7d62e33291
Make processor FUs unique for given itinerary. This extends the limit of 32
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FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
llvm-svn: 101754
2010-04-18 20:31:01 +00:00
1fd5fdaa7b
Add ARMv6 itineraries.
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llvm-svn: 89218
2009-11-18 18:39:57 +00:00
afcaf79603
Checkpoint NEON scheduling itineraries.
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llvm-svn: 82657
2009-09-23 21:38:08 +00:00
5090273367
Add Cortex-A8 VFP model.
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llvm-svn: 82483
2009-09-21 20:52:17 +00:00
a7c2dfbca1
Update Cortex-A8 instruction itineraries for integer instructions.
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llvm-svn: 79436
2009-08-19 18:00:44 +00:00
6ddd7bcdd1
Turn on if-conversion for thumb2.
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llvm-svn: 79084
2009-08-15 07:59:10 +00:00
a9c2aad939
Finalize itineraries for cortex-a8 integer multiply
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llvm-svn: 78908
2009-08-13 15:51:13 +00:00
fd5defed1d
Allow a zero cycle stage to reserve/require a FU without advancing the cycle counter.
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llvm-svn: 78736
2009-08-11 22:38:43 +00:00
62e053b790
Checkpoint scheduling itinerary changes.
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llvm-svn: 78564
2009-08-10 15:56:13 +00:00
f206d925a5
Fix comment.
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llvm-svn: 76693
2009-07-21 23:54:22 +00:00
4e712de541
Latency information for ARM v6. It's rough and not yet hooked up. Right now we are only using branch latency to determine if-conversion limits.
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llvm-svn: 73747
2009-06-19 01:51:50 +00:00
Andrew Trick