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3473 Commits

Author SHA1 Message Date
Chris Lattner d27b05e54a give better error diagnostics, for example: 
t.s:1:14: error: invalid operand for instruction
vldr.64	d17, [r0]   
       	     ^

instead of:

t.s:1:1: error: unrecognized instruction
vldr.64	d17, [r0]   
^

llvm-svn: 117611
 2010-10-28 21:41:58 +00:00
Chris Lattner f20f79808e hook up getOpcodeName for ARM so that "llc -show-mc-inst" includes 
the opcode string in the inst dump, e.g.:
	vmov	r2, r3, d17             @ encoding: [0x31,0x2b,0x53,0xec]
                                        @ <MCInst #989 VMOVRRD
                                        @  <MCOperand Reg:68>
                                        @  <MCOperand Reg:69>
                                        @  <MCOperand Reg:19>
                                        @  <MCOperand Imm:14>
                                        @  <MCOperand Reg:0>>

The "VMOVRRD" is new.

llvm-svn: 117609
 2010-10-28 21:37:33 +00:00
Chris Lattner 9487de6160 move a method out of line. 
llvm-svn: 117605
 2010-10-28 21:28:01 +00:00
Chris Lattner 9f9f4ebf0c remove the rest of hte owningptr's, no functionality change. 
llvm-svn: 117603
 2010-10-28 20:52:15 +00:00
Jim Grosbach 505607e4c6 PLD, PLDW, PLI encodings, plus refactor their use of addrmode2. 
llvm-svn: 117571
 2010-10-28 18:34:10 +00:00
Chris Lattner b24ba7be49 rearrange ParseRegisterList. 
llvm-svn: 117560
 2010-10-28 17:23:41 +00:00
Chris Lattner bd7c9fa36b refactor some code to simplify it, eliminating some owningptr's. 
llvm-svn: 117559
 2010-10-28 17:20:03 +00:00
Evan Cheng ff310737e5 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
llvm-svn: 117531
 2010-10-28 06:47:08 +00:00
Evan Cheng e2c211c1b9 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
llvm-svn: 117520
 2010-10-28 02:00:25 +00:00
Evan Cheng ff1c862f8e - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
 2010-10-28 01:49:06 +00:00
Owen Anderson 2ef668840a Add correct NEON encodings for vtbl and vtbx. 
llvm-svn: 117513
 2010-10-28 00:18:46 +00:00
Owen Anderson 14be930317 Add correct NEON encodings for vext, vtrn, vuzp, and vzip. 
llvm-svn: 117512
 2010-10-27 23:56:39 +00:00
Bob Wilson 6c55007edb Fix compiler warnings about signed/unsigned comparisons. 
llvm-svn: 117511
 2010-10-27 23:49:00 +00:00
Evan Cheng 59bbc545e0 Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
 2010-10-27 23:41:30 +00:00
Jim Grosbach 338de3ee56 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Owen Anderson fadb951e5b Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Jim Grosbach 055de2c789 Trailing whitespace 
llvm-svn: 117496
 2010-10-27 21:39:08 +00:00
Owen Anderson ed9652f959 Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Jim Grosbach f4ea7084c5 JIT imm12 encoding for constant pool entry references. 
llvm-svn: 117483
 2010-10-27 20:39:40 +00:00
Bob Wilson c7334a146e SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482
 2010-10-27 20:38:28 +00:00
Jim Grosbach 333b0a9e74 ARM JIT fix for LDRi12 and company. 
llvm-svn: 117478
 2010-10-27 19:55:59 +00:00
Owen Anderson 40d24a4abf Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Jim Grosbach ba1c6cd62f The new LDR* instruction patterns should handle the necessary encoding of 
operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

llvm-svn: 117461
 2010-10-27 17:52:51 +00:00
Owen Anderson 8576a42cf3 Add correct NEON encodings for vsli and vsri. 
llvm-svn: 117459
 2010-10-27 17:40:08 +00:00
Owen Anderson d7e8135e1e Add correct NEON encodings for vsra and vrsra. 
llvm-svn: 117458
 2010-10-27 17:29:29 +00:00
Jim Grosbach 8bf1483a3d The immediate operands of an LDRi12 instruction doesn't need the addrmode2 
encoding tricks. Handle the 'imm doesn't fit in the insn' case.

llvm-svn: 117454
 2010-10-27 16:50:31 +00:00
Jim Grosbach 9d2d1f0f00 LDRi12 machine instructions handle negative offset operands normally (simple 
integer values), not with the addrmode2 encoding.

llvm-svn: 117429
 2010-10-27 01:19:41 +00:00
Jim Grosbach 2577b2e8b1 One more spot where the new arm mode LDR instruction representation 
doesn't need the additional addrmode2 register operand. Missed it the first
time around.

llvm-svn: 117421
 2010-10-27 00:38:16 +00:00
Jim Grosbach 5a7c715470 Split ARM::LDRB into LDRBi12 and LDRBrs. Adjust accordingly. Continuing on 
rdar://8477752.

llvm-svn: 117419
 2010-10-27 00:19:44 +00:00
Jim Grosbach a92801b695 Since I parameterized this bit, I should probably actually use said parameter. 
llvm-svn: 117418
 2010-10-26 23:58:04 +00:00
Owen Anderson 825b2d1946 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
llvm-svn: 117411
 2010-10-26 22:50:46 +00:00
Jim Grosbach 1e4d9a17c2 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Owen Anderson 2888e2c7f9 Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
llvm-svn: 117402
 2010-10-26 21:58:41 +00:00
Owen Anderson e18579976f Simplify classes for shift instructions, which are never commutable. 
llvm-svn: 117398
 2010-10-26 21:13:59 +00:00
Owen Anderson 3665fee8de Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Jim Grosbach 9302bfdd5a Grammar. 
llvm-svn: 117388
 2010-10-26 19:34:41 +00:00
Jim Grosbach 79b3bf4d81 Nuke extraneous comment. It's applicable elsewhere, but not in this func. 
llvm-svn: 117387
 2010-10-26 19:22:23 +00:00
Owen Anderson 691ce68d3c Add correct NEON encoding for vpadal. 
llvm-svn: 117380
 2010-10-26 18:18:03 +00:00
Owen Anderson 284cb361d1 Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00
Evan Cheng e96b8d7ab6 Use instruction itinerary to determine what instructions are 'cheap'. 
llvm-svn: 117348
 2010-10-26 02:08:50 +00:00
Evan Cheng b45591979b NEON vmov's are in Neon domain. 
llvm-svn: 117347
 2010-10-26 02:03:05 +00:00
Bob Wilson 59f7cdaf98 Tidy up redundant check. 
llvm-svn: 117331
 2010-10-26 00:02:19 +00:00
Rafael Espindola d9d0c348df Produce the headers directly in the Finish method. This allows us to use 
the existing streamer methods that are endian safe.

llvm-svn: 117323
 2010-10-25 22:26:55 +00:00
Owen Anderson 1f6aad053d Add correct encodings for NEON vabal. 
llvm-svn: 117315
 2010-10-25 21:29:04 +00:00
Owen Anderson b9c91679aa Add correct NEON encodings for vaba. 
llvm-svn: 117309
 2010-10-25 20:52:57 +00:00
Owen Anderson dd001b89d7 Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment. 
llvm-svn: 117294
 2010-10-25 20:17:22 +00:00
Owen Anderson dea09c7564 Provide correct NEON encodings for vbsl. 
llvm-svn: 117293
 2010-10-25 20:13:13 +00:00
Jim Grosbach e6fe1a03c7 imm12 operands aren't Thumb2 only, so rename the printer helper function. 
llvm-svn: 117291
 2010-10-25 20:00:01 +00:00
Owen Anderson 2477446ee5 Add correct instruction encodings for vbic, vorn, and vmvn. 
llvm-svn: 117282
 2010-10-25 18:43:52 +00:00
Rafael Espindola 752913d6ba Add a virtual destructor. 
llvm-svn: 117280
 2010-10-25 18:38:32 +00:00