Commit Graph

6335 Commits

Author SHA1 Message Date
Daniel Sanders 7e52367398 [globalisel][tablegen] Import signextload and zeroextload.
Allow a pattern rewriter to be installed in CodeGenDAGPatterns and use it to
correct situations where SelectionDAG and GlobalISel disagree on
representation. For example, it would rewrite:
  (sextload:i32 $ptr)<<unindexedload>><<sextload>><<sextloadi16>
to:
  (sext:i32 (load:i16 $ptr)<<unindexedload>>)

I'd have preferred to replace the fragments and have the expansion happen
naturally as part of PatFrag expansion but the type inferencing system can't
cope with loads of types narrower than those mentioned in register classes.
This is because the SDTCisInt's on the sext constrain both the result and
operand to the 'legal' integer types (where legal is defined as 'a register
class can contain the type') which immediately rules the narrower types out.
Several targets (those with only one legal integer type) would then go on to
crash on the SDTCisOpSmallerThanOp<> when it removes all the possible types
for the result of the extend.

Also, improve isObviouslySafeToFold() slightly to automatically return true for
neighbouring instructions. There can't be any re-ordering problems if
re-ordering isn't happenning. We'll need to improve it further to handle
sign/zero-extending loads when the extend and load aren't immediate neighbours
though.

llvm-svn: 317971
2017-11-11 03:23:44 +00:00
Zachary Turner c631ba5f52 Update test_debuginfo.pl script to point to new tree location.
llvm-svn: 317949
2017-11-10 23:13:14 +00:00
Zachary Turner 0f2ce11df7 [debuginfo-tests] Make debuginfo-tests work in a standard configuration.
Previously, debuginfo-tests was expected to be checked out into
clang/test and then the tests would automatically run as part of
check-clang.  This is not a standard workflow for handling
external projects, and it brings with it some serious drawbacks
such as the inability to depend on things other than clang, which
we will need going forward.

The goal of this patch is to migrate towards a more standard
workflow.  To ease the transition for build bot maintainers,
this patch tries not to break the existing workflow, but instead
simply deprecate it to give maintainers a chance to update
the build infrastructure.

Differential Revision: https://reviews.llvm.org/D39605

llvm-svn: 317925
2017-11-10 20:57:57 +00:00
Krzysztof Parzyszek b8c68c67dc Allow separation of declarations and definitions in <Target>ISelDAGToDAG.inc
This patch adds the ability to include the member function declarations
in the instruction selector class separately from the member bodies.

Defining GET_DAGISEL_DECL macro to any value will only include the member
declarations. To include bodies, define GET_DAGISEL_BODY macro to be the
selector class name. Example:

  class FooDAGToDAGISel : public SelectionDAGISel {
    // Pull in declarations only.
    #define GET_DAGISEL_DECL
    #include "FooISelDAGToDAG.inc"
  };

  // Include the function bodies (with names qualified with the provided
  // class name).
  #define GET_DAGISEL_BODY FooDAGToDAGISel
  #include "FooISelDAGToDAG.inc"

When neither of the two macros are defined, the function bodies are emitted
inline (in the same way as before this patch).

Differential Revision: https://reviews.llvm.org/D39596

llvm-svn: 317903
2017-11-10 18:36:04 +00:00
Alex Bradbury 2af11919eb [utils] Fix RISC-V support in update_llc_test_checks.py
scrub_asm_riscv now takes two arguments rather than one.

llvm-svn: 317826
2017-11-09 20:01:25 +00:00
Alex Bradbury 86f971ccd6 [utils] Add RISC-V support to update_llc_test_checks.py
This should be a trivial change, and I've started using it for generating all 
tests at https://github.com/lowrisc/riscv-llvm (i.e. it's been tested in 
action quite a lot). Note that the regex does not attempt to match 
.cfi_startproc, as I want to ensure compatibility with functions that have the 
nounwind attribute.

Differential Revision: https://reviews.llvm.org/D39789

llvm-svn: 317693
2017-11-08 14:24:42 +00:00
Alexander Richardson 46e1fd6102 Add a -D flag to FileCheck to define variables
Summary:
This makes it very easy to test files that only differ in a constant
value somewhere in the test case.

Reviewers: jlebar, hfinkel, chandlerc, probinson

Reviewed By: probinson

Subscribers: probinson, llvm-commits

Differential Revision: https://reviews.llvm.org/D39629

llvm-svn: 317572
2017-11-07 13:24:44 +00:00
Florian Hahn 603c6455d2 [AArch64][SVE] Asm: Extend EnforceVectorSubVectorTypeIs to distinguish Scalable Vectors
Patch [1/5] in a series to add assembler/disassembler support for AArch64 SVE
unpredicated ADD/SUB instructions.

Patch by Sander De Smalen.

Reviewed by: rengolin

Differential Revision: https://reviews.llvm.org/D39087

llvm-svn: 317564
2017-11-07 10:43:56 +00:00
Justin Bogner f7b1007345 update_mir_test_checks: Be careful about replacing entire vregs
Previously, this could end up replacing a vreg like %14 with
[[VREG1]]4, where VREG1 was the match for %1. That's obviously not
correct, though it hasn't actually come up in any tests I've converted
so far.

llvm-svn: 317509
2017-11-06 21:06:09 +00:00
Aaron Ballman cbaf5a4f50 Move the llvm-tblgen project into the Tablegenning folder on IDEs like Visual Studio rather than leave it in the root directory. NFC.
llvm-svn: 317420
2017-11-04 20:07:16 +00:00
Craig Topper e5d44cefea [X86] Teach EVEX->VEX pass to turn SHUFI32X4/SHUFF32X4/SHUFI64X/SHUFF64X2 into VPERM2F128/VPERM2I128.
This recovers some of the tests that were changed by r317403.

llvm-svn: 317410
2017-11-04 18:10:03 +00:00
Diana Picus d1b618177a [globalisel][tablegen] Skip src child predicates
The GlobalISel TableGen backend didn't check for predicates on the
source children. This caused it to generate code for ARM patterns such
as SMLABB or similar, but without properly checking for the sext_16_node
part of the operands. This in turn meant that we would select SMLABB
instead of MLA for simple sequences such as s32 + s32 * s32, which is
wrong (we want a MLA on the full operands, not just their bottom 16
bits).

This patch forces TableGen to skip patterns with predicates on the src
children, so it doesn't generate code for SMLABB and other similar ARM
instructions at all anymore. AArch64 and X86 are not affected.

Differential Revision: https://reviews.llvm.org/D39554

llvm-svn: 317313
2017-11-03 10:30:19 +00:00
Craig Topper 2fda36a18e [TableGen] Add an extra blank line to DAGISel output file to separate functions.
llvm-svn: 317298
2017-11-03 05:19:34 +00:00
Daniel Sanders 466fe399b8 [globalisel][regbank] Warn about MIR ambiguities when register bank/class names clash.
llvm-svn: 317132
2017-11-01 22:13:05 +00:00
Craig Topper 4e56ba271e [X86] Add custom code to EVEX to VEX pass to turn unmasked 128-bit VPALIGND/Q into VPALIGNR if the extended registers aren't being used.
This will enable us to prefer VALIGND/Q during shuffle lowering in order to get the extended register encoding space when BWI isn't available. But if we end up not using the extended registers we can switch VPALIGNR for the shorter VEX encoding.

Differential Revision: https://reviews.llvm.org/D39401

llvm-svn: 317122
2017-11-01 21:00:59 +00:00
Daniel Sanders 9cbe7c7f93 [globalisel][tablegen] Add support for multi-insn emission
The importer will now accept nested instructions in the result pattern such as
(ADDWrr $a, (SUBWrr $b, $c)). This is only valid when the nested instruction
def's a single vreg and the parent instruction consumes a single vreg where a
nested instruction is specified. The importer will automatically create a vreg
to connect the two using the type information from the pattern. This vreg will
be constrained to the register classes given in the instruction definitions*.

* REG_SEQUENCE is explicitly rejected because of this. The definition doesn't
  constrain to a register class and it therefore needs special handling.

llvm-svn: 317117
2017-11-01 19:57:57 +00:00
NAKAMURA Takumi 1657f2ad99 Fix warnings discovered by rL317076. [-Wunused-private-field]
llvm-svn: 317091
2017-11-01 13:47:55 +00:00
Daniel Sanders 198447a447 [globalisel][tablegen] Stop hard-coding the emitted instruction ID to 0. NFC
The next commit will add support for multi-instruction emission so we need to
start allocating instruction ID's instead of hard-coding them to 0.

llvm-svn: 317057
2017-11-01 00:29:47 +00:00
Jake Ehrlich cde781015f Add system-linux to allow tests run with llvm-lit to restrict themselves to linux
I need a test that only runs in a reasonable amount of time on systems
that have sparse files. The broadest class of systems that support
sparse files are linux systems. So restricting my test to linux systems
should suffice. This change adds the system-linux feature to llvm-lit so
that it can be required.

Differential Revision: https://reviews.llvm.org/D39482

llvm-svn: 317055
2017-11-01 00:18:51 +00:00
Daniel Sanders 7438b26317 Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
(ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.

The previous commit failed on the Ubuntu bots using GCC 4.8. These bots lack the
const_iterator forms of insert() and emplace() that were added in C++11. As a
result I've switched the const_iterators to iterators.

llvm-svn: 317049
2017-10-31 23:03:18 +00:00
Daniel Sanders f69d1b018c Revert r317040: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
The same bots fail but I believe I know what the issue is now. These bots are
missing the const_iterator versions of insert/emplace/etc. that were introduced
in C++11.

llvm-svn: 317042
2017-10-31 21:54:52 +00:00
Daniel Sanders 374f71ac90 Re-commit: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
 (ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.

The previous commit failed on the Ubuntu bots using GCC 4.8. These bots didn't
like a call to emplace(). I've replaced it with insert() to see if it's a quirk
of the C++11 support.

llvm-svn: 317040
2017-10-31 21:34:53 +00:00
Daniel Sanders f87c142d9e Revert r317029: [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
The Linux bots don't seem to like this usage of emplace(). Reverting while I look into it.

llvm-svn: 317033
2017-10-31 20:29:28 +00:00
Daniel Sanders e8a4f0d869 [globalisel][tablegen] Keep track of the insertion point while adding BuildMIAction's. NFC
Multi-instruction emission needs to ensure the the instructions are generated
a depth-first fashion. For example:
  (ADDWrr (SUBWrr a, b), c)
needs to emit the SUBWrr before the ADDWrr. However, our walk over
TreePatternNode's is highly context sensitive which makes it difficult to append
BuildMIActions in the order we want. To fix this, we now keep track of the
insertion point as we add actions. This will allow multi-insn emission to insert
BuildMI's in the correct place.

llvm-svn: 317029
2017-10-31 19:54:05 +00:00
Daniel Sanders df258e328a [globalisel][tablegen] Factor out implicit def/use renderers from createAndImportInstructionRenderer(). NFC
Multi-instruction emission will require that we have separate handling for
the defs between the implicitly created temporaries and the rule outputs.
The former require new temporary vregs while the latter should copy existing
operands. Factor out the implicit def/use renderers to minimize the code
duplication when we implement that.

llvm-svn: 317025
2017-10-31 19:09:29 +00:00
Daniel Sanders a7b7526416 [globalisel][tablegen] Add infrastructure to potentially allow BuildMIAction to choose a mutatable instruction. NFC
Prepare for multiple instruction emission by allowing BuildMIAction to
search for a suitable matcher that will support mutation.

This patch deliberately neglects to add matchers aside from the root to
preserve NFC. That said, it should be noted that until we support mutations
other than just the opcode the chances of finding a non-root instruction
for which canMutate() is true, is essentially zero. Furthermore in the
presence of multi-instruction emission the chances of finding any
instruction for which canMutate() is true is also zero. Nevertheless, we
can't continue to require that all BuildMIAction's consider the root of the match
to be recyclable due to the risk of recycling it twice in the same rule.

llvm-svn: 317022
2017-10-31 18:50:24 +00:00
Daniel Sanders 6ea17edd80 [globalisel][tablegen] Allow any comment in DebugCommentAction. NFC
llvm-svn: 317017
2017-10-31 18:07:03 +00:00
Ayman Musa 25589e2a55 Adding a shufflevector and select LLVM IR instructions fuzz tool
Based on similar python tool - utils/shuffle-fuzz.py - this tool extends the ability of it's previous by optionally attaching select instruction to the generated shufflevector instructions.
This was mainly developed to perform exhaustive testing of the X86 AVX512 masked shuffle instructions. But yet it can be used for various other targets.
The general design of the implementation is much modular than the original shuffle_fuzz.py tool, which makes it easier for anyone to extend it further.

Differential Revision: https://reviews.llvm.org/D38031

Change-Id: I0efc2aaa091b61a8a9552311c21cc77916a97111
llvm-svn: 316989
2017-10-31 11:39:31 +00:00
Zachary Turner 94f5032aed Force #define GTEST_LANG_CXX11.
gtest depends on this #define to determine whether it can
use various classes like std::tuple, or whether it has to fall
back to experimental classes in the std::tr1 namespace.  The
check in the current version of gtest relies on the value of
the `__cplusplus` macro, but MSVC provides a non-conformant
value of this macro, making it effectively impossible to detect
C++11.  In short, LLVM compiled with MSVC has been silently
using the tr1 versions of several classes since the beginning of
time.

This would normally be pretty benign, except that in the latest
preview of MSVC they have marked all of the tr1 classes
deprecated, so it spews thousands of warnings.

llvm-svn: 316798
2017-10-27 21:12:28 +00:00
Craig Topper 01ebd9b7f7 [TableGen] Use Twine instead of std::string concatenation in two calls to PrintFatalError.
llvm-svn: 316697
2017-10-26 20:49:36 +00:00
Craig Topper 0551556ed2 [AsmParser][TableGen] Add VariantID argument to the generated mnemonic spell check function so it can use the correct table based on variant.
I'm considering implementing the mnemonic spell checker for x86, and that would require the separate intel and att variants.

llvm-svn: 316641
2017-10-26 06:46:41 +00:00
Craig Topper 2a06028c0a [AsmParser][TableGen] Make the generated mnemonic spell checker function a file local static function.
Also only emit in targets that specificially request it. This is required so we don't get an unused static function error.

llvm-svn: 316640
2017-10-26 06:46:40 +00:00
Daniel Sanders ab1d119154 [globalisel][tablegen] Fix future undefined behaviour in r316463.
I missed a dereference of `Matched` that preceeded the new check. Thanks to
Justin Bogner for spotting it.

llvm-svn: 316480
2017-10-24 18:11:54 +00:00
Daniel Sanders 64f745cf20 [globalisel][tablegen] Multi-insn emission requires that BuildMIAction support not being linked to an InstructionMatcher. NFC
When multi-instruction emission is supported, it will no longer be guaranteed
that every BuildMIAction has a corresponding matched instruction. BuildMIAction
should support not having one to cover the case where a rule produces more
instructions than it matched.

llvm-svn: 316463
2017-10-24 17:08:43 +00:00
Craig Topper 194cb74dec [TableGen] Fix some formatting quirks in the subtarget output file.
llvm-svn: 316450
2017-10-24 15:50:55 +00:00
Craig Topper df1285b8f4 [TableGen] Simplify some of the subtarget emission by removing code that avoids printing commas at the end of arrays and enums.
The C++ standard allows for trailing commas. We already do this in many other emitters.

llvm-svn: 316449
2017-10-24 15:50:53 +00:00
Sanjay Patel 9db5da2b63 [utils] make retq/retl regex an option that is off by default
Ideally, we should compare 32- and 64-bit versions to see if the 
ret line is the only difference and then insert the regex only
in that case. But this is a quick hack to avoid a bunch of noise
as existing tests are updated.

llvm-svn: 316443
2017-10-24 14:32:52 +00:00
Daniel Sanders bd83ad4a87 [globalisel][tablegen] Remove unused InstructionMatcher's. NFC
llvm-svn: 316407
2017-10-24 01:48:34 +00:00
Daniel Sanders d66e0901ae [globalisel][tablegen] Import stores and allow GISel to automatically substitute zero regs like WZR/XZR/$zero.
This patch enables the import of stores. Unfortunately, doing so by itself,
loses an optimization where storing 0 to memory makes use of WZR/XZR.

To mitigate this, this patch also introduces a new feature that allows register
operands to nominate a zero register. When this is done, GlobalISel will
substitute (G_CONSTANT 0) with the nominated register automatically. This
is currently configured to only apply to the stores.

Applying it to GPR32/GPR64 register classes in general will be done after
review see (https://reviews.llvm.org/D39150).

llvm-svn: 316360
2017-10-23 18:19:24 +00:00
Craig Topper e06cc6d9ba [X86] Fix disassembler table generation to prevent instructions tagged with 'PS' being inherited into PD/XS/XD attribute entries.
llvm-svn: 316345
2017-10-23 16:49:26 +00:00
Craig Topper 64cb997ce1 [X86] Update a doxygen comment in the disassembler tablegen code. NFC
llvm-svn: 316309
2017-10-23 03:42:35 +00:00
Craig Topper 326008c615 [X86] Fix disassembly of EVEX rounding control and SAE instructions.
Fixes PR31955.

llvm-svn: 316308
2017-10-23 02:26:24 +00:00
Fangrui Song dc168722da [utils] Support -mtriple=powerpc64
Summary: test/CodeGen/PowerPC/pr33093.ll uses both powerpc64 (big-endian) and powerpc64le while the former was unsupported.

Subscribers: nemanjai

Differential Revision: https://reviews.llvm.org/D39164

llvm-svn: 316297
2017-10-22 18:43:23 +00:00
Craig Topper dac20263a1 [X86] More correctly support LIG and WIG for EVEX instructions in the disassembler tables.
This is similar to how we generate the VEX tables.

More fixes are still needed for the instructions that use EVEX.b (broadcast and embedded rounding).

llvm-svn: 316294
2017-10-22 17:22:29 +00:00
Craig Topper e975127db6 [X86] Teach the disassembler that some instructions use VEX.W==0 without a corresponding VEX.W==1 instruction and we shouldn't treat them as if VEX.W is ignored.
Fixes PR11304.

llvm-svn: 316285
2017-10-22 06:18:26 +00:00
Craig Topper ca2382d809 [X86] Fix disassembling of EVEX instructions to stop accidentally decoding the SIB index register as an XMM/YMM/ZMM register.
This introduces a new operand type to encode the whether the index register should be XMM/YMM/ZMM. And new code to fixup the results created by readSIB.

This has the nice effect of removing a bunch of code that hard coded the name of every GATHER and SCATTER instruction to map the index type.

This fixes PR32807.

llvm-svn: 316273
2017-10-21 20:03:20 +00:00
Sanjay Patel f1735a58ed [utils, x86] add regex for retl/retq to reduce duplicated FileChecking (PR35003)
llvm-svn: 316242
2017-10-20 21:55:23 +00:00
Daniel Sanders 1e4569fdc1 [globalisel][tablegen] Fix small spelling nits. NFC
ComplexRendererFn -> ComplexRendererFns
Corrected a couple lingering references to tied operands that were missed.

llvm-svn: 316237
2017-10-20 20:55:29 +00:00
Justin Bogner da9600e646 update_mir_test_checks: Support adding checks for vreg classes
This is a temporary hack to support adding checks for the "registers:"
block of mir functions. This is necessary to convert a number of tests
so that there's less churn when we change the MIR printer to put the
vreg classes on defs instead of in their own block.

llvm-svn: 316134
2017-10-18 22:39:55 +00:00
Justin Bogner 6b55f1f513 update_mir_test_checks: Improve message when updating fails
llvm-svn: 316133
2017-10-18 22:36:08 +00:00