84e7967fae
Add codegen support for NEON vst4lane intrinsics with 128-bit vectors.
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llvm-svn: 83600
2009-10-09 00:01:36 +00:00
c409030838
Add codegen support for NEON vst3lane intrinsics with 128-bit vectors.
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llvm-svn: 83598
2009-10-08 23:51:31 +00:00
b851eb356a
Add codegen support for NEON vst2lane intrinsics with 128-bit vectors.
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llvm-svn: 83596
2009-10-08 23:38:24 +00:00
38ba47225a
Add codegen support for NEON vld4lane intrinsics with 128-bit vectors.
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Also fix some copy-and-paste errors in previous changes.
llvm-svn: 83590
2009-10-08 22:53:57 +00:00
cf54e934f8
Add codegen support for NEON vld3lane intrinsics with 128-bit vectors.
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llvm-svn: 83585
2009-10-08 22:27:33 +00:00
222b86cd54
Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair.
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llvm-svn: 83572
2009-10-08 20:43:22 +00:00
c2728f44a9
Add codegen support for NEON vld2lane intrinsics with 128-bit vectors.
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llvm-svn: 83568
2009-10-08 18:56:10 +00:00
fac9476589
Clean up some unnecessary initializations.
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llvm-svn: 83566
2009-10-08 18:52:56 +00:00
4facd965bd
Clean up a comment (indentation was wrong).
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llvm-svn: 83565
2009-10-08 18:51:31 +00:00
02fda54e8f
Add missing names for the XCore specific LADD and LSUB nodes.
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llvm-svn: 83556
2009-10-08 17:14:57 +00:00
4e13316bf9
Add some peepholes for signed comparisons using ashr X, X, 32.
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llvm-svn: 83549
2009-10-08 15:38:17 +00:00
b6b0ab6117
Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83526
2009-10-08 05:18:18 +00:00
534ea5ae32
Cleanup up unused R3LiveIn tracking.
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llvm-svn: 83522
2009-10-08 01:50:26 +00:00
c0615aa17f
Re-enable register scavenging in Thumb1 by default.
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llvm-svn: 83521
2009-10-08 01:46:59 +00:00
71387b4b2f
Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83518
2009-10-08 00:28:28 +00:00
d4f5670096
Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83513
2009-10-08 00:21:01 +00:00
32cc4ec304
Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors.
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llvm-svn: 83508
2009-10-07 23:54:04 +00:00
5ef3c6d9f4
Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors.
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llvm-svn: 83506
2009-10-07 23:39:57 +00:00
763be1a248
Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors.
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llvm-svn: 83502
2009-10-07 22:57:01 +00:00
456735c54b
reverting thumb1 scavenging default due to test failure while I figure out what's up.
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llvm-svn: 83501
2009-10-07 22:49:41 +00:00
e32fe29d29
Fix handling of x86 'R' constraint.
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llvm-svn: 83499
2009-10-07 22:47:20 +00:00
37cf79e5a6
Enable thumb1 register scavenging by default.
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llvm-svn: 83494
2009-10-07 22:26:14 +00:00
50820a2677
Add some instruction encoding bits for NEON load/store instructions.
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llvm-svn: 83490
2009-10-07 21:53:04 +00:00
e7ef4a9a6b
Add codegen support for NEON vst4 intrinsics with 128-bit vectors.
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llvm-svn: 83486
2009-10-07 20:49:18 +00:00
23464866ad
Add codegen support for NEON vst3 intrinsics with 128-bit vectors.
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llvm-svn: 83484
2009-10-07 20:30:08 +00:00
3dcb5377ef
Add codegen support for NEON vst2 intrinsics with 128-bit vectors.
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llvm-svn: 83482
2009-10-07 18:47:39 +00:00
ab3a9474d6
Add codegen support for NEON vld4 intrinsics with 128-bit vectors.
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llvm-svn: 83479
2009-10-07 18:09:32 +00:00
2207e5fc7b
Add another bit of the ARM target assembler to llvm-mc to parse registers
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with writeback, things like "sp!", etc. Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.
llvm-svn: 83477
2009-10-07 18:01:35 +00:00
be8137b0b4
Replace TargetInstrInfo::isInvariantLoad and its target-specific
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implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.
llvm-svn: 83475
2009-10-07 17:38:06 +00:00
6bbefc2f67
Add codegen support for NEON vld3 intrinsics with 128-bit vectors.
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llvm-svn: 83471
2009-10-07 17:24:55 +00:00
99e80228a9
Rearrange code for selecting vld2 intrinsics. No functionality change.
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This is just to be more consistent with the forthcoming code for vld3/4.
llvm-svn: 83470
2009-10-07 17:23:09 +00:00
fa14dd430c
Add register-reuse to frame-index register scavenging. When a target uses
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a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.
eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.
ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.
llvm-svn: 83467
2009-10-07 17:12:56 +00:00
75b59fb055
Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar)
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and register spills.
llvm-svn: 83435
2009-10-07 00:06:35 +00:00
febe39b488
Added bits of the ARM target assembler to llvm-mc to parse some load instruction
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operands. Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts. This is a work in progress.
llvm-svn: 83424
2009-10-06 22:26:42 +00:00
e6b778d5ff
Add codegen support for NEON vld2 operations on quad registers.
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llvm-svn: 83422
2009-10-06 22:01:59 +00:00
74b3d284f2
Use copyRegToReg hook to copy registers.
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llvm-svn: 83421
2009-10-06 22:01:15 +00:00
dc7d1ce575
Fix a comment typo.
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Patch by Johnny Chen.
llvm-svn: 83407
2009-10-06 20:18:46 +00:00
10d3dc569b
Instead of printing unnecessary basic block labels as labels in
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verbose-asm mode, print comments instead. This eliminates a non-comment
difference between verbose-asm mode and non-verbose-asm mode.
Also, factor out the relevant code out of all the targets and into
target-independent code.
llvm-svn: 83392
2009-10-06 17:38:38 +00:00
692f6e7f9d
Remove xs1b predicate since it is no longer needed to differentiate betweem
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xs1a and xs1b.
llvm-svn: 83383
2009-10-06 16:17:57 +00:00
d7b887410d
Remove xs1a subtarget. xs1a is a preproduction device used in
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early development boards which is no longer supported in the
XMOS toolchain.
llvm-svn: 83381
2009-10-06 16:01:09 +00:00
29e8555056
Default to the xs1b subtarget
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llvm-svn: 83380
2009-10-06 15:41:52 +00:00
051454a16f
Update processDebugLoc() so that it can be used to process debug info before and after printing an instruction.
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llvm-svn: 83363
2009-10-06 02:19:11 +00:00
2dfb5da6bb
In Thumb1, the register scavenger is not always able to use an emergency
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spill slot. When frame references are via the frame pointer, they will be
negative, but Thumb1 load/store instructions only allow positive immediate
offsets. Instead, Thumb1 will spill to R12.
llvm-svn: 83336
2009-10-05 22:30:23 +00:00
2728569a38
Remove explicit enum integer values. They don't appear to be needed, and
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they make it less convenient to add new entries.
llvm-svn: 83308
2009-10-05 15:52:08 +00:00
774149a878
Add RIP to GR64_NOREX. This fixed a MachineVerifier error when RIP
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is used in an operand which requires GR64_NOREX.
llvm-svn: 83307
2009-10-05 15:42:08 +00:00
fdd8790718
strength reduce a ton of type equality tests to check the typeid (Through
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the new predicates I added) instead of going through a context and doing a
pointer comparison. Besides being cheaper, this allows a smart compiler
to turn the if sequence into a switch.
llvm-svn: 83297
2009-10-05 05:54:46 +00:00
d76b9b766c
Add a comment to describe letters used in multiclass name suffixes.
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llvm-svn: 83257
2009-10-03 04:44:16 +00:00
a9abf57409
Fix encoding problem for VMLS instruction.
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Thanks to Johnny Chen for pointing this out!
llvm-svn: 83256
2009-10-03 04:41:21 +00:00
32a47ea7b6
getFunctionAlignment should return log2 alignment.
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llvm-svn: 83242
2009-10-02 06:57:25 +00:00
b659dff4eb
Forgot about ARM::tPUSH. It also has a new writeback operand.
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llvm-svn: 83237
2009-10-02 05:03:07 +00:00
Bob Wilson