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111 Commits

Author SHA1 Message Date
Vincent Lejeune 4b8d9e303c R600: Workaround for cayman loop bug 
llvm-svn: 196121
 2013-12-02 17:29:37 +00:00
Tom Stellard 4d566b2edf R600: Add support for ISD::FROUND 
NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195878
 2013-11-27 21:23:20 +00:00
Tom Stellard c0845334da R600/SI: Fixing handling of condition codes 
We were ignoring the ordered/onordered bits and also the signed/unsigned
bits of condition codes when lowering the DAG to MachineInstrs.

NOTE: This is a candidate for the 3.4 branch.
llvm-svn: 195514
 2013-11-22 23:07:58 +00:00
Tom Stellard 81d871dee3 R600/SI: Add support for private address space load/store 
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.

llvm-svn: 194626
 2013-11-13 23:36:50 +00:00
Vincent Lejeune f143af3fe9 R600: Use function inputs to represent data stored in gpr 
llvm-svn: 194425
 2013-11-11 22:10:24 +00:00
Vincent Lejeune 533352f696 R600: Clear the VPM bit of export instructions. 
It makes apparently no change it to set this bit or not but the
docs recommand to left it cleared.

llvm-svn: 192552
 2013-10-13 17:55:57 +00:00
Vincent Lejeune 6df39438af R600: Add a ldptr intrinsic to support MSAA. 
llvm-svn: 191838
 2013-10-02 16:00:33 +00:00
Vincent Lejeune a4da6fb535 R600: add a pass that merges clauses. 
llvm-svn: 191790
 2013-10-01 19:32:58 +00:00
Vincent Lejeune 269708b98d R600: Enable -verify-machineinstrs in some tests. 
llvm-svn: 191788
 2013-10-01 19:32:38 +00:00
Tom Stellard 0351ea2010 R600: Fix handling of NAN in comparison instructions 
We were completely ignoring the unorder/ordered attributes of condition
codes and also incorrectly lowering seto and setuo.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 191603
 2013-09-28 02:50:50 +00:00
Tom Stellard cd42818d86 SelectionDAG: Try to expand all condition codes using getCCSwappedOperands() 
This is useful for targets like R600, which only support GT, GE, NE, and EQ
condition codes as it removes the need to handle unsupported condition
codes in target specific code.

There are no tests with this commit, but R600 has been updated to take
advantage of this new feature, so its existing selectcc tests are now
testing the swapped operands path.

llvm-svn: 191601
 2013-09-28 02:50:38 +00:00
Aaron Watry 372cecf642 R600: Add support for LDS atomic subtract 
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 190200
 2013-09-06 20:17:42 +00:00
Tom Stellard 13c68ef88b R600: Add support for local memory atomic add 
llvm-svn: 190080
 2013-09-05 18:38:09 +00:00
Vincent Lejeune 4d5c5e53d0 R600: Use SchedModel enum for is{Trans,Vector}Only functions 
llvm-svn: 189979
 2013-09-04 19:53:30 +00:00
Tom Stellard c6f4a29ed5 R600: Add support for i8 and i16 local memory loads 
llvm-svn: 189225
 2013-08-26 15:05:59 +00:00
Tom Stellard f3d166aa1e R600: Add support for i8 and i16 local memory stores 
llvm-svn: 189223
 2013-08-26 15:05:49 +00:00
Tom Stellard d3ee8c103a R600: Add support for i16 and i8 global stores 
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188519
 2013-08-16 01:12:06 +00:00
Tom Stellard 6d1379e180 R600: Add support for v4i32 stores on Cayman 
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188518
 2013-08-16 01:12:00 +00:00
Tom Stellard 676c16d088 R600: Add IsExport bit to TableGen instruction definitions 
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188516
 2013-08-16 01:11:51 +00:00
Tom Stellard ac00f9df79 R600: Change the RAT instruction assembly names so they match the docs 
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188515
 2013-08-16 01:11:46 +00:00
Tom Stellard 3494b7ee42 R600/SI: Handle MSAA texture targets 
Patch by: Marek Olšák

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 188421
 2013-08-14 22:22:14 +00:00
Tom Stellard 0344cdfe39 R600: Add 64-bit float load/store support 
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions

Tom Stellard:
  - Mark vec2 operations as expand.  The addition of a vec2 register
    class made them all legal.

Patch by: Dmitry Cherkassov

Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
llvm-svn: 187582
 2013-08-01 15:23:42 +00:00
Tom Stellard 4dd41845ec Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions" 
This reverts commit 3f1de26cb5cc0543a6a1d71259a7a39d97139051.

llvm-svn: 187524
 2013-07-31 20:43:03 +00:00
Vincent Lejeune 79afe17e99 R600: Use SchedModel enum for is{Trans,Vector}Only functions 
llvm-svn: 187512
 2013-07-31 19:31:35 +00:00
Vincent Lejeune 0c5ed2b437 R600: Remove predicated_break inst 
We were using two instructions for similar purpose : break and
predicated break. Only predicated_break was emitted and it was
lowered at R600ControlFlowFinalizer to JUMP;CF_BREAK;POP.
This commit simplify the situation by making AMDILCFGStructurizer
emit IF_PREDICATE;BREAK;ENDIF; instead of predicated_break (which
is now removed).

There is no functionality change.

llvm-svn: 187510
 2013-07-31 19:31:14 +00:00
Tom Stellard 8cb0e47c9e R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary 
These are really the same address space in hardware.  The only
difference is that CONSTANT_ADDRESS uses a special cache for faster
access.  When we are unable to use the constant kcache for some reason
(e.g. smaller types or lack of indirect addressing) then the instruction
selector must use GLOBAL_ADDRESS loads instead.

llvm-svn: 187006
 2013-07-23 23:54:56 +00:00
Tom Stellard 5263948a7b R600: Add support for 24-bit MAD instructions 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186923
 2013-07-23 01:48:49 +00:00
Tom Stellard 41fc7853be R600: Add support for 24-bit MUL instructions 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186922
 2013-07-23 01:48:42 +00:00
Tom Stellard 9f95033d33 R600: Improve support for < 32-bit loads 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186921
 2013-07-23 01:48:35 +00:00
Tom Stellard 1e80309ebe R600: Use KCache for kernel arguments 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186918
 2013-07-23 01:48:18 +00:00
Tom Stellard 33dd04bfbe R600: Clean up extended load patterns 
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
llvm-svn: 186914
 2013-07-23 01:47:52 +00:00
Vincent Lejeune 8b8a7b5514 R600: Don't emit empty then clause and use alu_pop_after 
llvm-svn: 186725
 2013-07-19 21:45:15 +00:00
Vincent Lejeune ce499744b3 R600: Do not predicated basic block with multiple alu clause 
Test is not included as it is several 1000 lines long.
To test this functionnality, a test case must generate at least 2 ALU clauses,
where an ALU clause is ~110 instructions long.

NOTE: This is a candidate for the stable branch.
llvm-svn: 185943
 2013-07-09 15:03:33 +00:00
Vincent Lejeune b55940cc7d R600: Use DAG lowering pass to handle fcos/fsin 
NOTE: This is a candidate for the stable branch.
llvm-svn: 185940
 2013-07-09 15:03:11 +00:00
Vincent Lejeune f10d1cd2a3 R600: Print Export Swizzle 
llvm-svn: 185939
 2013-07-09 15:03:03 +00:00
Vincent Lejeune 77a8352476 R600: Support schedule and packetization of trans-only inst 
llvm-svn: 185268
 2013-06-29 19:32:43 +00:00
Tom Stellard c026e8bc8e R600: Add local memory support via LDS 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185162
 2013-06-28 15:47:08 +00:00
Tom Stellard ce540330df R600: Add support for GROUP_BARRIER instruction 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185161
 2013-06-28 15:46:59 +00:00
Tom Stellard 5eb903d9c5 R600: Add ALUInst bit to tablegen definitions v2 
v2:
  - Remove functions left over from a previous rebase.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185160
 2013-06-28 15:46:53 +00:00
Tom Stellard 02661d9605 R600: Use new getNamedOperandIdx function generated by TableGen 
llvm-svn: 184880
 2013-06-25 21:22:18 +00:00
Tom Stellard 9810ec613c R600: Add support for i32 loads from the constant address space on Cayman 
Tested-By: Aaron Watry <awatry@gmail.com>
llvm-svn: 184821
 2013-06-25 02:39:30 +00:00
Aaron Watry 52a72c926c R600: Fix spelling error in comment 
our -> or

llvm-svn: 184756
 2013-06-24 16:57:57 +00:00
Vincent Lejeune 8bd10421ec R600: Properly set COUNT_3 bit in TEX clause initiating inst for pre EG gen. 
Fixes rv7x0 bug in Heaven reported here:
https://bugs.freedesktop.org/show_bug.cgi?id=64257

llvm-svn: 184116
 2013-06-17 20:16:26 +00:00
Tom Stellard ecf9d86404 R600: Use correct encoding for Vertex Fetch instructions on Cayman 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184016
 2013-06-14 22:12:30 +00:00
Tom Stellard 6aa0d5578d R600: Use EXPORT_RAT_INST_STORE_DWORD for stores on Cayman 
We were using RAT_INST_STORE_RAW, which seemed to work, but the docs
say this instruction doesn't exist for Cayman, so it's probably safer
to use a documented instruction instead.

Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184015
 2013-06-14 22:12:24 +00:00
Tom Stellard d99b7932ae R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184014
 2013-06-14 22:12:19 +00:00
Tom Stellard 3d0823f1cd R600: Move instruction encoding definitions into a separate .td file 
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184013
 2013-06-14 22:12:09 +00:00
Tom Stellard a6c6e1bfc2 R600: Rework subtarget info and remove AMDILDevice classes 
This should simplify the subtarget definitions and make it easier to
add new ones.

Reviewed-by: Vincent Lejeune <vljn@ovi.com>
llvm-svn: 183566
 2013-06-07 20:37:48 +00:00
Vincent Lejeune a09873dda7 R600: Constraints input regs of interp_xy,_zw 
llvm-svn: 183106
 2013-06-03 15:44:16 +00:00
Tom Stellard 5643c4ac72 R600: Swap the legality of rotl and rotr 
The hardware supports rotr and not rotl.

llvm-svn: 182285
 2013-05-20 15:02:19 +00:00