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84 Commits

Author SHA1 Message Date
Krzysztof Parzyszek f63ad39e7d [Hexagon] Handle a global operand to A2_addi when creating duplexes 
llvm-svn: 306012
 2017-06-22 15:53:31 +00:00
Krzysztof Parzyszek 57a8bb4343 [Hexagon] Change iconst to emit 27bit relocation 
Patch by Colin LeMahieu.

llvm-svn: 301956
 2017-05-02 18:19:11 +00:00
Krzysztof Parzyszek a750383d0f [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCREL 
Patch by Sid Manning.

llvm-svn: 301955
 2017-05-02 18:15:33 +00:00
Krzysztof Parzyszek b0af1ef741 [Hexagon] Make sure duplexed dealloc_returns are checked for double jumps 
Patch by Colin LeMahieu.

llvm-svn: 301951
 2017-05-02 18:03:08 +00:00
Krzysztof Parzyszek 49f7e0a98b [Hexagon] Move checking AXOK to checker 
Patch by Colin LeMahieu.

llvm-svn: 301949
 2017-05-02 18:00:37 +00:00
Krzysztof Parzyszek c15f8d2a08 [Hexagon] Extract function that checks endloops with other branches 
Change location number to point to conflicting branch instruction.

Patch by Colin LeMahieu.

llvm-svn: 301946
 2017-05-02 17:56:11 +00:00
Krzysztof Parzyszek 55db483a46 [Hexagon] Improving error reporting for writing to read only registers 
Patch by Colin LeMahieu.

llvm-svn: 301828
 2017-05-01 20:10:41 +00:00
Krzysztof Parzyszek e96d27a997 [Hexagon] Give better error messages for solo instruction errors 
Patch by Colin LeMahieu.

llvm-svn: 301827
 2017-05-01 20:06:01 +00:00
Colin LeMahieu 553ec588ae [Hexagon] Fixing test from 297920 to add Hexagon triple. 
llvm-svn: 297926
 2017-03-16 01:52:10 +00:00
Colin LeMahieu ddebad956e [Hexagon] Updating inline saturate lanes for v62 version. 
llvm-svn: 297920
 2017-03-16 00:35:28 +00:00
Krzysztof Parzyszek 5f4dedffd4 [Hexagon] Fix testcase accidentally broken by r296645 
llvm-svn: 296647
 2017-03-01 17:53:42 +00:00
Krzysztof Parzyszek f9015e62fd [Hexagon] Introduce Hexagon V62 
llvm-svn: 294805
 2017-02-10 23:46:45 +00:00
Krzysztof Parzyszek a72fad980c [Hexagon] Replace instruction definitions with auto-generated ones 
llvm-svn: 294753
 2017-02-10 15:33:13 +00:00
Krzysztof Parzyszek c8d676ef72 [Hexagon] Remove encoding bits from mapped instructions 
- Map A2_zxtb to A2_andir.
- Map PS_call_nr J2_call.
- Map A2_tfr[t|f][new] to A2_padd[t|f][new].
    
Patch by Colin LeMahieu.

llvm-svn: 294320
 2017-02-07 17:42:11 +00:00
Krzysztof Parzyszek 5b4a6b67c5 [Hexagon] Adding gp+ to the syntax of gp-relative instructions 
Patch by Colin LeMahieu.

llvm-svn: 294258
 2017-02-06 23:18:57 +00:00
Krzysztof Parzyszek 8cdfe8ecf3 [Hexagon] Update MCTargetDesc 
Changes include:
- Updates to the instruction descriptor flags.
- Improvements to the packet shuffler and checker.
- Updates to the handling of certain relocations.
- Better handling of duplex instructions.

llvm-svn: 294226
 2017-02-06 19:35:46 +00:00
Krzysztof Parzyszek d0d42f0ec8 [Hexagon] Adding opExtentBits and opExtentAlign to GPrel instructions 
Patch by Colin LeMahieu.

llvm-svn: 293933
 2017-02-02 20:35:12 +00:00
Krzysztof Parzyszek e17b0bfb24 [Hexagon] Fix relocation kind for extended predicated calls 
Patch by Sid Manning.

llvm-svn: 293931
 2017-02-02 20:21:56 +00:00
Krzysztof Parzyszek 73e0ad8220 [Hexagon] Fix disassembler crash after r279255 
When p0 was added as an explicit operand to the duplex subinstructions,
the disassembler was not updated to reflect this.

llvm-svn: 281104
 2016-09-09 21:45:00 +00:00
Daniel Sanders 8e3c74210f Remove redundant -mattr options from llvm-objdump commands. 
The -mattr options in these four tests have no effect on the output of
llvm-objdump. In the case of the two Mips tests, removing the -mattr option
left duplicate RUN lines so the duplicates have been removed.

llvm-svn: 272906
 2016-06-16 15:47:19 +00:00
Krzysztof Parzyszek a053101c95 [Hexagon] Use pipe instead of temporary files in tests 
llvm-svn: 270217
 2016-05-20 14:01:34 +00:00
Krzysztof Parzyszek 7c7bb538cb [Hexagon] Treat all conditional branches as predicted (not-taken by default) 
llvm-svn: 268946
 2016-05-09 18:22:07 +00:00
Krzysztof Parzyszek f7a4bd4068 [Hexagon] Add aliases for vector loads/stores with no explicit offset 
The mem(r0) instructions are treated as mem(r0+#0).

llvm-svn: 268661
 2016-05-05 18:38:35 +00:00
Krzysztof Parzyszek e5fcce2d2b [Hexagon] Add instruction aliases for vector unsigned compare-equal 
Unsigned compare-equal instructions are mapped to signed compare-equal.

llvm-svn: 267925
 2016-04-28 19:49:18 +00:00
Krzysztof Parzyszek 0e7d2d339d [Hexagon] Define certain aliases for vector instructions 
Specifically:
  Vd = #0   -> Vd = vxor(Vd, Vd)
  Vdd = #0  -> Vdd.w = vsub(Vdd.w, Vdd.w)
  Vdd = Vss -> Vdd = vcombine(Vss.H, Vss.L)

llvm-svn: 267901
 2016-04-28 16:43:16 +00:00
Krzysztof Parzyszek e737b86f8c [Hexagon] Handle double-vector registers as new-value producers 
Patch by Colin LeMahieu.

llvm-svn: 267897
 2016-04-28 15:54:48 +00:00
Colin LeMahieu a3782da3e3 [Hexagon] Merging nops in to previous packet rather than always creating a new one. 
llvm-svn: 267798
 2016-04-27 21:37:44 +00:00
Krzysztof Parzyszek a4602b5be1 [Hexagon] Use llvm-mc instead of llc in an MC testcase 
Remember to svn add the new file.

llvm-svn: 267435
 2016-04-25 18:09:36 +00:00
Krzysztof Parzyszek 4ea9bd72df [Hexagon] Use llvm-mc instead of llc in an MC testcase 
llvm-svn: 267434
 2016-04-25 18:08:33 +00:00
Krzysztof Parzyszek e6ee481bdf [Hexagon] Correctly set "Flags" in ELF header 
llvm-svn: 267397
 2016-04-25 12:49:47 +00:00
Krzysztof Parzyszek e2c6405708 [Hexagon] Add definitions for trap/pause instructions 
Also add tests for other instructions from HexagonSystemInst.td.

llvm-svn: 267162
 2016-04-22 16:25:00 +00:00
Krzysztof Parzyszek adf02ae540 [Hexagon] Properly recognize register alt names 
llvm-svn: 267038
 2016-04-21 19:49:53 +00:00
Krzysztof Parzyszek 5626703837 [Hexagon] Fix handling of lcomm directive 
Patch by Colin LeMahieu.

llvm-svn: 266882
 2016-04-20 15:54:13 +00:00
Colin LeMahieu efe3732883 Revert r265817 
lld tests need to be addressed.

llvm-svn: 265822
 2016-04-08 18:15:37 +00:00
Colin LeMahieu 4a1975ba8e [llvm-objdump] Printing hex instead of dec by default 
Differential Revision: http://reviews.llvm.org/D18770

llvm-svn: 265817
 2016-04-08 17:55:03 +00:00
Krzysztof Parzyszek b14f4fd0de [Hexagon] Add handling fixups and instruction relaxation 
llvm-svn: 263981
 2016-03-21 20:27:17 +00:00
Krzysztof Parzyszek c6f1e1a709 [Hexagon] Properly encode registers in duplex instructions 
llvm-svn: 263980
 2016-03-21 20:13:33 +00:00
Colin LeMahieu ab9eca4d9f [Hexagon] As a size optimization, not lazy extending TPREL or DTPREL variants since they're usually in range. 
llvm-svn: 262258
 2016-02-29 21:21:56 +00:00
Colin LeMahieu ecef1d9cbc [Hexagon] Adding relocation for code size, cold path optimization allowing a 23-bit 4-byte aligned relocation to be a valid instruction encoding. 
The usual way to get a 32-bit relocation is to use a constant extender which doubles the size of the instruction, 4 bytes to 8 bytes.

Another way is to put a .word32 and mix code and data within a function.  The disadvantage is it's not a valid instruction encoding and jumping over it causes prefetch stalls inside the hardware.

This relocation packs a 23-bit value in to an "r0 = add(rX, #a)" instruction by overwriting the source register bits.  Since r0 is the return value register, if this instruction is placed after a function call which return void, r0 will be filled with an undefined value, the prefetch won't be confused, and the callee can access the constant value by way of the link register.

llvm-svn: 261006
 2016-02-16 20:38:17 +00:00
Hemant Kulkarni d8a985ec7c [llvm-readobj] Option to emit readelf like output 
New option --elf-output-style=LLVM or GNU
Enables -file-headers in readelf style when elf-output-style=GNU

Differential revision: http://reviews.llvm.org/D14128

llvm-svn: 260430
 2016-02-10 20:40:55 +00:00
Hemant Kulkarni f46c92fe52 Revert "[llvm-readobj] Option to emit readelf like output" 
This reverts commit a58765909660a7195b32e0cc8c7476168b913750.

llvm-svn: 260397
 2016-02-10 18:21:01 +00:00
Hemant Kulkarni 4f2ca0d268 [llvm-readobj] Option to emit readelf like output 
New option --elf-output-style=LLVM or GNU
Enables -file-headers in readelf style when elf-output-style=GNU

Differential revision: http://reviews.llvm.org/D14128

llvm-svn: 260391
 2016-02-10 17:51:28 +00:00
Colin LeMahieu 1c79d9be6e [Hexagon] Fixing relocation generation and adding tests. 
llvm-svn: 260259
 2016-02-09 19:18:02 +00:00
Dimitry Andric 227b928abc Fix several accidental DOS line endings in source files 
Summary:
There are a number of files in the tree which have been accidentally checked in with DOS line endings.  Convert these to native line endings.

There are also a few files which have DOS line endings on purpose, and I have set the svn:eol-style property to 'CRLF' on those.

Reviewers: joerg, aaron.ballman

Subscribers: aaron.ballman, sanjoy, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D15848

llvm-svn: 256707
 2016-01-03 17:22:03 +00:00
Krzysztof Parzyszek 21dc8bdd9e [Hexagon] Add PIC support 
llvm-svn: 256025
 2015-12-18 20:19:30 +00:00
Colin LeMahieu 15ca65c253 [Hexagon] Adding shuffling resources for HVX instructions and tests for instruction encodings. 
llvm-svn: 254652
 2015-12-03 21:44:28 +00:00
Colin LeMahieu fa5558307b [Hexagon] NFC. Adding a number of packet correctness tests. 
llvm-svn: 253000
 2015-11-13 01:46:06 +00:00
Colin LeMahieu 8bb168b160 [Hexagon] Adding relaxation functionality to backend and test. 
llvm-svn: 252989
 2015-11-13 01:12:25 +00:00
Colin LeMahieu 7a92c6ecbb [Hexagon] Adding checks for values out of operand range and correct new-value producer usage. 
llvm-svn: 252969
 2015-11-12 23:28:01 +00:00
Colin LeMahieu a1fa71ead9 [Hexagon] Adding test to make sure labels and register pairs are correctly parsed. 
llvm-svn: 252968
 2015-11-12 22:54:14 +00:00