Commit Graph

18903 Commits

Author SHA1 Message Date
Will Dietz 981af0021b Add missing #include's to cctype when using isdigit/alpha/etc.
llvm-svn: 192519
2013-10-12 00:55:57 +00:00
Andrew Kaylor 7bb1344c67 Adding multiple object support to MCJIT EH frame handling
llvm-svn: 192504
2013-10-11 21:25:48 +00:00
Matthias Braun 5bfee00dfa Introduce ad hoc liveness tracking utility: LiveRegUnits
Contains a set of live register (units) and code to move forward and
backward in the schedule while updating the live set.

llvm-svn: 192481
2013-10-11 19:04:35 +00:00
Quentin Colombet de0e06234c [DAGCombiner] Reapply load slicing (192471) with a test that explicitly set sse4.2 support.
This should fix the buildbots.

Original commit message:
[DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.

E.g., this optimization will transform something like this:
a = load i64* addr
b = trunc i64 a to i32
c = lshr i64 a, 32
d = trunc i64 c to i32

into:
b = load i32* addr1
d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.

One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.

<rdar://problem/14477220>

llvm-svn: 192476
2013-10-11 18:29:42 +00:00
Quentin Colombet 5aee63d9e3 [DAGCombiner] Revert load slicing (r192471), until I figure out why it fails on ubuntu.
llvm-svn: 192474
2013-10-11 18:17:17 +00:00
Quentin Colombet 41dc258f71 [DAGCombiner] Slice a big load in two loads when the element are next to each
other in memory and the target has paired load and performs post-isel loads
combining.

E.g., this optimization will transform something like this:
 a = load i64* addr
 b = trunc i64 a to i32
 c = lshr i64 a, 32
 d = trunc i64 c to i32

into:
 b = load i32* addr1
 d = load i32* addr2
Where addr1 = addr2 +/- sizeof(i32), if the target supports paired load and
performs post-isel loads combining.

One should overload TargetLowering::hasPairedLoad to provide this information.
The default is false.

<rdar://problem/14477220>

llvm-svn: 192471
2013-10-11 18:01:14 +00:00
Justin Holewinski 660597d190 Make AsmPrinter::emitImplicitDef a virtual method so targets can emit custom comments for implicit defs
For NVPTX, this fixes a crash where the emitImplicitDef implementation was expecting physical registers,
while NVPTX uses virtual registers (with a couple of exceptions).  Now, the implicit def comment will be
emitted as a true PTX register name. Other targets can use this to customize the output of implicit def
comments.

Fixes PR17519

llvm-svn: 192444
2013-10-11 12:39:36 +00:00
Matthias Braun f6fe6bfffe Print register in LiveInterval::print()
llvm-svn: 192398
2013-10-10 21:29:05 +00:00
Matthias Braun 34e1be9451 Represent RegUnit liveness with LiveRange instance
Previously LiveInterval has been used, but having a spill weight and
register number is unnecessary for a register unit.

llvm-svn: 192397
2013-10-10 21:29:02 +00:00
Matthias Braun 2d5c32b3b5 Work on LiveRange instead of LiveInterval where possible
Also change some pointer arguments to references at some places where
0-pointers are not allowed.

llvm-svn: 192396
2013-10-10 21:28:57 +00:00
Matthias Braun 88dd0abd2d Pass LiveQueryResult by value
This makes the API a bit more natural to use and makes it easier to make
LiveRanges implementation details private.

llvm-svn: 192394
2013-10-10 21:28:52 +00:00
Matthias Braun d7df935bbc Refactor LiveInterval: introduce new LiveRange class
LiveRange just manages a list of segments and a list of value numbers
now as LiveInterval did previously, but without having details like spill
weight or a fixed register number.
LiveInterval is now a subclass of LiveRange and simply adds the spill weight
and the register number.

llvm-svn: 192393
2013-10-10 21:28:47 +00:00
Matthias Braun 13ddb7cd65 Rename LiveRange to LiveInterval::Segment
The Segment struct contains a single interval; multiple instances of this struct
are used to construct a live range, but the struct is not a live range by
itself.

llvm-svn: 192392
2013-10-10 21:28:43 +00:00
Matthias Braun 1965bfa4c7 Rename parameter: defined regs are not incoming.
llvm-svn: 192391
2013-10-10 21:28:38 +00:00
Sriram Murali 34e37f0cc7 test commit
- fix comments on vector type legalization

llvm-svn: 192389
2013-10-10 20:24:53 +00:00
Matt Arsenault 668e38a40b Fix grammar / missing words
llvm-svn: 192380
2013-10-10 18:47:35 +00:00
Manman Ren c50fa1114b Debug Info: In DIBuilder, the context field of subprogram is updated to use
DIScopeRef.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192378
2013-10-10 18:40:01 +00:00
Hao Liu 99eac7ee44 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192361
2013-10-10 17:00:52 +00:00
Rafael Espindola 9558af461d Revert "Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem). Including following 14 instructions: 4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers. ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4). 4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers. st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4)."
This reverts commit r192352. It broke the build.

llvm-svn: 192354
2013-10-10 15:15:17 +00:00
Hao Liu 9123ad8ab9 Implement AArch64 vector load/store multiple N-element structure class SIMD(lselem).
Including following 14 instructions:
4 ld1 insts: load multiple 1-element structure to sequential 1/2/3/4 registers.
ld2/ld3/ld4: load multiple N-element structure to sequential N registers (N=2,3,4).
4 st1 insts: store multiple 1-element structure from sequential 1/2/3/4 registers.
st2/st3/st4: store multiple N-element structure from sequential N registers (N = 2,3,4).

llvm-svn: 192352
2013-10-10 15:01:24 +00:00
Rui Ueyama 82166eef16 Revert "llvm-c: Make target initializer functions external functions in lib."
This reverts commit r192316. The original change introduced circular
dependencies between libTarget and backends. That would broke a build unless
link everything into one big binary.

llvm-svn: 192329
2013-10-09 23:15:49 +00:00
Manman Ren 88b0f948f5 Debug Info: In DIBuilder, the context and type fields of template_type and
template_value are updated to use DIRef.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192320
2013-10-09 19:46:28 +00:00
Anders Waldenborg d39827d4a4 llvm-c: Make target initializer functions external functions in lib.
Making them proper functions defined in the (shared)lib instead of
static inlines defined in the header files makes it possible to
actually distribute a binary compiled against the shared library
without having to worry about getting undefined symbol errors when
calling e.g LLVMInitializeAllTargetInfos because the shared library on
the other system was compiled with different targets.

Differential Revision: http://llvm-reviews.chandlerc.com/D1714

llvm-svn: 192316
2013-10-09 19:02:09 +00:00
Benjamin Kramer 4188293c72 Flip the ownership of MCStreamer and MCTargetStreamer.
MCStreamer now owns the target streamer. This prevents leaking the target
streamer.

llvm-svn: 192303
2013-10-09 17:23:41 +00:00
Rafael Espindola caa435664a Add a GlobalAlias::isValidLinkage to reduce code duplication.
Thanks to Reid Kleckner for the suggestion.

llvm-svn: 192298
2013-10-09 16:07:32 +00:00
Elena Demikhovsky a3a714082b AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.
llvm-svn: 192283
2013-10-09 08:16:14 +00:00
Chad Rosier 9849cc6696 [AArch64] Add support for NEON scalar floating-point reciprocal estimate,
reciprocal exponent, and reciprocal square root estimate instructions.

llvm-svn: 192242
2013-10-08 22:09:04 +00:00
Matt Arsenault bfd1971bbb Fix duplicated assertions.
Do what some other instructions do, and add an assert method.

llvm-svn: 192236
2013-10-08 21:11:12 +00:00
Chad Rosier f7ed96ef76 [AArch64] Add support for NEON scalar signed/unsigned integer to floating-point
convert instructions.

llvm-svn: 192231
2013-10-08 20:43:30 +00:00
Reid Kleckner cd4a25d66e Explicitly request unsigned enum types when desired
This fixes repeated -Wmicrosoft warnings when self-hosting clang on
Windows, and gets us real unsigned enum types with MSVC.

llvm-svn: 192227
2013-10-08 20:15:11 +00:00
Manman Ren 235010a6d0 Move DIRef::getName out of line.
llvm-svn: 192214
2013-10-08 18:42:03 +00:00
Benjamin Kramer b32b1be766 IRBuilder: Downgrade InsertPointGuard's instruction pointer to a raw pointer.
Sadly this loses the checking from AssertingVH, but apparently storing the
end() of a BasicBlock into an AssertingVH has bad consequences as it's not
really an instruction.

llvm-svn: 192209
2013-10-08 17:44:56 +00:00
Rafael Espindola a17151ad5a Add a MCTargetStreamer interface.
This patch fixes an old FIXME by creating a MCTargetStreamer interface
and moving the target specific functions for ARM, Mips and PPC to it.

The ARM streamer is still declared in a common place because it is
used from lib/CodeGen/ARMException.cpp, but the Mips and PPC are
completely hidden in the corresponding Target directories.

I will send an email to llvmdev with instructions on how to use this.

llvm-svn: 192181
2013-10-08 13:08:17 +00:00
Nick Kledzik 733c77fd86 update mach-o EXPORT_SYMBOL_* names
llvm-svn: 192151
2013-10-08 00:59:13 +00:00
Richard Mitton 0aafb58aca Formally added an explicit enum for DWARF TLS support. No functionality change.
llvm-svn: 192118
2013-10-07 18:39:18 +00:00
Matt Arsenault fbcbce439d Change objectsize intrinsic to accept different address spaces.
Bitcasting everything to i8* won't work. Autoupgrade the old
intrinsic declarations to use the new mangling.

llvm-svn: 192117
2013-10-07 18:06:48 +00:00
Rafael Espindola 7ef22b84c8 Remove dead code.
Support for exception handling in the legacy JIT was removed in r181354 and
this code was dead since then.

Thanks to Yaron Keren for noticing it.

llvm-svn: 192101
2013-10-07 13:54:50 +00:00
Rafael Espindola 41d630f448 Fix the documentation of getDefaultSubtargetFeatures.
Patch by David Nadlinger.

llvm-svn: 192098
2013-10-07 13:34:05 +00:00
David Majnemer 61eae2e30c Revert "Revert "Windows: Add support for unicode command lines""
This reverts commit r192070 which reverted r192069, I forgot to
regenerate the configure scripts.

llvm-svn: 192079
2013-10-07 01:00:07 +00:00
David Majnemer f636cf422e Revert "Windows: Add support for unicode command lines"
This is causing MinGW bots to fail.
This reverts commit r192069.

llvm-svn: 192070
2013-10-06 20:44:34 +00:00
David Majnemer 80bea0c315 Windows: Add support for unicode command lines
Summary:
The MSVCRT deliberately sends main() code-page specific characters.
This isn't too useful to LLVM as we end up converting the arguments to
UTF-16 and subsequently attempt to use the result as, for example, a
file name.  Instead, we need to have the ability to access the Unicode
command line and transform it to UTF-8.

This has the distinct advantage over using the MSVC-specific wmain()
function as our entry point because:
 - It doesn't work on cygwin.
 - It only work on MinGW with caveats and only then on certain versions.
 - We get to keep our entry point as main(). :)

N.B.  This patch includes fixes to other parts of lib/Support/Windows
s.t. we would be able to take advantage of getting the Unicode paths.
E.G.  clang spawning clang -cc1 would want to give it Unicode arguments.

Reviewers: aaron.ballman, Bigcheese, rnk, ruiu

Reviewed By: rnk

CC: llvm-commits, ygao

Differential Revision: http://llvm-reviews.chandlerc.com/D1834

llvm-svn: 192069
2013-10-06 20:25:49 +00:00
Elena Demikhovsky 2e408aefe0 AVX-512: added scalar convert instructions and intrinsics.
Fixed load folding in VPERM2I instruction.

llvm-svn: 192063
2013-10-06 13:11:09 +00:00
Simon Atanasyan 567f085177 [Mips] Add MIPS program header types.
llvm-svn: 192059
2013-10-06 08:49:41 +00:00
Craig Topper 52196640a2 Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient.
llvm-svn: 192039
2013-10-05 19:22:59 +00:00
Rafael Espindola ac4ad25a00 Remove some really nasty uses of hasRawTextSupport.
When MC was first added, targets could use hasRawTextSupport to keep features
working before they were added to the MC interface.

The design goal of MC is to provide an uniform api for printing assembly and
object files. Short of relaxations and other corner cases, a object file is
just another representation of the assembly.

It was never the intention that targets would keep doing things like

if (hasRawTextSupport())
  Set flags in one way.
else
  Set flags in another way.

When they do that they create two code paths and the object file is no longer
just another representation of the assembly. This also then requires testing
with llc -filetype=obj, which is extremelly brittle.

This patch removes some of these hacks by replacing them with smaller ones.
The ARM flag setting is trivial, so I just moved it to the constructor. For
Mips, the patch adds two temporary hack directives that allow the assembly
to represent the same things as the object file was already able to.

The hope is that the mips developers will replace the hack directives with
the same ones that gas uses and drop the -print-hack-directives flag.

I will also try to implement a target streamer interface, so that we can
move this out of the common code.

In summary, for any new work, two rules of the thumb are
  * Don't use "llc -filetype=obj" in tests.
  * Don't add calls to hasRawTextSupport.

llvm-svn: 192035
2013-10-05 16:42:21 +00:00
Jiangning Liu ad242fbb71 Implement aarch64 neon instruction set AdvSIMD (Across).
llvm-svn: 192028
2013-10-05 08:22:10 +00:00
Craig Topper a1bbc323fa Add OPC_CheckChildSame0-3 to the DAG isel matcher. This replaces sequences of MoveChild, CheckSame, MoveParent. Saves 846 bytes from the X86 DAG isel matcher, ~300 from ARM, ~840 from Hexagon.
llvm-svn: 192026
2013-10-05 05:38:16 +00:00
Manman Ren b3388601fb Debug Info: In DIBuilder, the derived-from field of a DW_TAG_pointer_type
is updated to use DITypeRef.

Move isUnsignedDIType and getOriginalTypeSize from DebugInfo.h to be static
helper functions in DwarfCompileUnit. We already have a static helper function
"isTypeSigned" in DwarfCompileUnit, and a pointer to DwarfDebug is added to
resolve the derived-from field. All three functions need to go across link
for derived-from fields, so we need to get hold of a type identifier map.

A pointer to DwarfDebug is also added to DbgVariable in order to resolve the
derived-from field.

Debug info verifier is updated to check a derived-from field is a TypeRef.
Verifier will not go across link for derived-from fields, in debug info finder,
we go across the link to add derived-from fields to types.

Function getDICompositeType is only used by dragonegg and since dragonegg does
not generate identifier for types, we use an empty map to resolve the
derived-from field.

When printing a derived-from field, we use DITypeRef::getName to either return
the type identifier or getName of the DIType.

A paired commit at clang is required due to changes to DIBuilder.

llvm-svn: 192018
2013-10-05 01:43:03 +00:00
Eric Christopher fc917c6208 Pull this out for a bit of readability.
llvm-svn: 191999
2013-10-04 23:35:30 +00:00
Eric Christopher 53a3e69cfe Reformat.
llvm-svn: 191997
2013-10-04 23:15:52 +00:00