Commit Graph

321743 Commits

Author SHA1 Message Date
Peter Wu fa52e00c85 [Sema] Suppress additional warnings for C's zero initializer
Summary:
D28148 relaxed some checks for assigning { 0 } to a structure for all C
standards, but it failed to handle structures with non-integer
subobjects. Relax -Wmissing-braces checks for such structures, and add
some additional tests.

This fixes PR39931.

Patch By: al3xtjames

Reviewed By: Lekensteyn

Differential Revision: https://reviews.llvm.org/D61838

llvm-svn: 366163
2019-07-16 01:13:36 +00:00
Michael Liao 543ba4e9e0 [InstructionSimplify] Apply sext/trunc after pointer stripping
Summary:
- As the pointer stripping could trace through `addrspacecast` now, need
  to sext/trunc the offset to ensure it has the same width as the
  pointer after stripping.

Reviewers: jdoerfert

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64768

llvm-svn: 366162
2019-07-16 01:03:06 +00:00
Alex Langford 0d12127318 [Target] Remove unused method Target::GetDefaultClangModuleSearchPaths
llvm-svn: 366161
2019-07-16 01:02:32 +00:00
Jonas Devlieghere 01ee172e9e Revert "[DebugInfo] Move function from line table to the prologue (NFC)"
This broke LLD, which I didn't have enabled.

llvm-svn: 366160
2019-07-16 00:59:04 +00:00
Nathan Lanza 50f0c82453 Allow for vendor prefixes in a list test
Summary:
Preprocessor/init.c contains a line that explicitly checks for the
string

__VERSION__ "Clang{{.*}}

It's valid to have a toolchain configured to emit a vendor prefix
before the word Clang. e.g.

__VERSION__ "Vendor Clang{{.*}}

Subscribers: fedor.sergeev, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64772

llvm-svn: 366159
2019-07-16 00:57:50 +00:00
Jonas Devlieghere 509903e887 [DebugInfo] Move function from line table to the prologue (NFC)
In LLDB, when parsing type units, we don't need to parse the whole line
table. Instead, we only need to parse the "support files" from the line
table prologue.

To make that possible, this patch moves the respective functions from
the LineTable into the Prologue. Because I don't think users of the
LineTable should have to know that these files come from the Prologue,

I've left the original methods in place, and made them redirect to the
LineTable.

Differential revision: https://reviews.llvm.org/D64774

llvm-svn: 366158
2019-07-16 00:37:17 +00:00
Eric Christopher bf20b2ace6 Temporarily revert "add -fthinlto-index= option to clang-cl"
This is causing testsuite failures on (at least) darwin release+asserts.

This reverts commit r366146.

llvm-svn: 366157
2019-07-16 00:02:40 +00:00
Jason Molenda c245249b7b Update some file changes, but there's a dependency loop so
it doesn't quite work rigtht now.

llvm-svn: 366156
2019-07-15 23:55:22 +00:00
Eric Christopher fdcbd5fa48 Temporarily Revert "fix unnamed fiefield issue and add tests for __builtin_preserve_access_index intrinsic"
The commit had tests that would only work with names in the IR.

This reverts commit r366076.

llvm-svn: 366155
2019-07-15 23:49:31 +00:00
Eric Christopher 93dfb93ad6 Temporarily Revert "[SLP] Recommit: Look-ahead operand reordering heuristic."
As there are some reported miscompiles with AVX512 and performance regressions
in Eigen. Verified with the original committer and testcases will be forthcoming.

This reverts commit r364964.

llvm-svn: 366154
2019-07-15 23:36:02 +00:00
Leonard Chan bb147aabc6 Revert "[NewPM] Port Sancov"
This reverts commit 5652f35817.

llvm-svn: 366153
2019-07-15 23:18:31 +00:00
Jan Korous 60a0d49e77 [DirectoryWatcher][linux] Fix for older kernels
IN_EXCL_UNLINK exists since Linux 2.6.36

Differential Revision: https://reviews.llvm.org/D64764

llvm-svn: 366152
2019-07-15 23:14:00 +00:00
Craig Topper 51193871da [X86] Teach convertToThreeAddress to handle SUB with immediate
We mostly avoid sub with immediate but there are a couple cases that can create them. One is the add 128, %rax -> sub -128, %rax trick in isel. The other is when a SUB immediate gets created for a compare where both the flags and the subtract value is used. If we are unable to linearize the SelectionDAG to satisfy the flag user and the sub result user from the same instruction, we will clone the sub immediate for the two uses. The one that produces flags will eventually become a compare. The other will have its flag output dead, and could then be considered for LEA creation.

I added additional test cases to add.ll to show the the sub -128 trick gets converted to LEA and a case where we don't need to convert it.

This showed up in the current codegen for PR42571.

Differential Revision: https://reviews.llvm.org/D64574

llvm-svn: 366151
2019-07-15 23:07:56 +00:00
Julian Lettner c48162db99 [TSan] Fix asm token error (again)
llvm-svn: 366150
2019-07-15 23:05:14 +00:00
Heejin Ahn 1cf6922660 [WebAssembly] Add missing utility methods for exnref type
Summary:
This adds missing utility methods and copy instruction handling for
`exnref` type and also adds tests.

`tee` instruction tests are missing because `isTee` is currently only
used in ExplicitLocals pass and testing that pass in mir requires
serialization of stackified registers in mir files, which is a bit
nontrivial because `MachineFunctionInfo` only has info of vreg numbers
(which are large integers) but not the mir's register numbers. But this
change is quite trivial anyway.

Reviewers: tlively

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64705

llvm-svn: 366149
2019-07-15 23:04:00 +00:00
Alex Langford b5701710a4 [LanguageRuntime] Move ObjCLanguageRuntime into a plugin
Summary:
Following up to my CPPLanguageRuntime change, I'm moving
ObjCLanguageRuntime into a plugin as well.

Reviewers: JDevlieghere, compnerd, jingham, clayborg

Subscribers: mgorny, arphaman, lldb-commits

Differential Revision: https://reviews.llvm.org/D64763

llvm-svn: 366148
2019-07-15 22:56:12 +00:00
Yuanfang Chen a28dcf693d [llvm-readelf] Print "File: lib.a(file.o)" info when dumping archive files.
Match GNU readelf.

https://bugs.llvm.org/show_bug.cgi?id=35351

Reviewers: jhenderson, grimar, MaskRay, rupprecht

Reviewed by: jhenderson, MaskRay, grimar

Differential Revision: https://reviews.llvm.org/D64361

llvm-svn: 366147
2019-07-15 22:52:01 +00:00
Bob Haarman 199f8721e6 add -fthinlto-index= option to clang-cl
Summary:
This adds a -fthinlto-index= option to clang-cl, which allows it to
be used to drive ThinLTO backend passes. This allows clang-cl to be
used for distributed ThinLTO.

Reviewers: tejohnson, pcc, rnk

Subscribers: mehdi_amini, steven_wu, dexonsmith, arphaman, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64458

llvm-svn: 366146
2019-07-15 22:50:04 +00:00
Heejin Ahn 9f96a58ccc [WebAssembly] Rename except_ref type to exnref
Summary:
We agreed to rename `except_ref` to `exnref` for consistency with other
reference types in
https://github.com/WebAssembly/exception-handling/issues/79. This also
renames WebAssemblyInstrExceptRef.td to WebAssemblyInstrRef.td in order
to use the file for other reference types in future.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, hiraditya, sunfish, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64703

llvm-svn: 366145
2019-07-15 22:49:25 +00:00
Shoaib Meenai c9e3c83014 Revert [llvm-lipo] Implement -create (with hardcoded alignments)
This reverts r366142 (git commit 67cee1dc7e)

The test is failing on the Windows buildbots. Reverting while I
investigate.

llvm-svn: 366144
2019-07-15 22:44:08 +00:00
Tom Stellard 4422cc4f1a [OpenCL] Make TableGen'd builtin tables and helper functions static
Reviewers: Pierre, Anastasia

Reviewed By: Anastasia

Subscribers: yaxunl, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64608

llvm-svn: 366143
2019-07-15 22:34:19 +00:00
Shoaib Meenai 67cee1dc7e [llvm-lipo] Implement -create (with hardcoded alignments)
Creates universal binary output file from input files. Currently uses
hard coded value for alignment.  Want to get the create functionality
approved before implementing the alignment function.

Patch by Anusha Basana <anusha.basana@gmail.com>

Differential Revision: https://reviews.llvm.org/D64102

llvm-svn: 366142
2019-07-15 22:29:30 +00:00
Lang Hames 853813293a [clang-fuzzer] Remove 'setUseOrcMCJITReplacement(false)' call.
The default value for this option (UseMCJITReplacement) is already false, and
OrcMCJITReplacement is going to have deprecation warnings attached in LLVM 9.0.
Removing this call removes a spurious warning.

llvm-svn: 366141
2019-07-15 22:27:57 +00:00
Heejin Ahn 474009eaea [WebAssembly] Simplify regcopy.mir
Summary:
This deletes the ll templates from the functions because they don't need
them (mir files need ll templates only when they have function calls or
BB names that are not numbers).

This also renames the filename to `reg-copy.mir`, because I'm planning
to add some more `reg-*.mir` soon.

Reviewers: tlively

Subscribers: dschuff, sbc100, jgravelle-google, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64704

llvm-svn: 366140
2019-07-15 22:22:10 +00:00
Wouter van Oortmerssen 292e21d8bc [WebAssembly] Assembler: support special floats: infinity / nan
Summary:
These are emitted as identifiers by the InstPrinter, so we should
parse them as such. These could potentially clash with symbols of
the same name, but that is out of our (the WebAssembly backend) control.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, aheejin, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64770

llvm-svn: 366139
2019-07-15 22:13:39 +00:00
Jan Korous c5e7a3d710 [DirectoryWatcher][test] Relax test assumptions
Workaround for FSEvents sometimes sending notifications for events that happened
before DirectoryWatcher was created.

This caused tests to be flaky on green dragon.

llvm-svn: 366138
2019-07-15 22:11:51 +00:00
Jan Korous 5076038bb0 [DirectoryWatcher][NFC][test] Add typedef for enum
llvm-svn: 366137
2019-07-15 22:11:28 +00:00
Matt Morehouse 8528b1951c [ASan] Fix >80 character line.
llvm-svn: 366136
2019-07-15 22:07:56 +00:00
Austin Kerbow 423b4a18a4 [AMDGPU] Enable merging m0 initializations.
Summary:
Enable hoisting and merging m0 defs that are initialized with the same
immediate value. Fixes bug where removed instructions are not considered
to interfere with other inits, and make sure to not hoist inits before block
prologues.

Reviewers: rampitec, arsenm

Reviewed By: rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64766

llvm-svn: 366135
2019-07-15 22:07:05 +00:00
Dominik Adamski 46b84fa231 [ScopInfo][NFC] Add dot at the end of comment statement.
llvm-svn: 366134
2019-07-15 22:01:55 +00:00
Simon Atanasyan becae2b232 [mips] Print BEQZL and BNEZL pseudo instructions
One of the reasons - to be compatible with GNU tools.

llvm-svn: 366133
2019-07-15 21:46:38 +00:00
Matt Arsenault b082f1055b AMDGPU: Use standalone MUBUF load patterns
We already do this for the flat and DS instructions, although it is
certainly uglier and more verbose.

This will allow using separate pattern definitions for extload and
zextload. Currently we get away with using a single PatFrag with
custom predicate code to check if the extension type is a zextload or
anyextload. The generic mechanism the global isel emitter understands
treats these as mutually exclusive. I was considering making the
pattern emitter accept zextload or sextload extensions for anyextload
patterns, but in global isel, the different extending loads have
distinct opcodes, and there is currently no mechanism for an opcode
matcher to try multiple (and there probably is very little need for
one beyond this case).

llvm-svn: 366132
2019-07-15 21:41:44 +00:00
Julian Lettner 228f80d92d [TSan] Fix asm token error
llvm-svn: 366131
2019-07-15 21:22:57 +00:00
Nick Desaulniers c4f245b40a [LoopUnroll+LoopUnswitch] do not transform loops containing callbr
Summary:
There is currently a correctness issue when unrolling loops containing
callbr's where their indirect targets are being updated correctly to the
newly created labels, but their operands are not.  This manifests in
unrolled loops where the second and subsequent copies of callbr
instructions have blockaddresses of the label from the first instance of
the unrolled loop, which would result in nonsensical runtime control
flow.

For now, conservatively do not unroll the loop.  In the future, I think
we can pursue unrolling such loops provided we transform the cloned
callbr's operands correctly.

Such a transform and its legalities are being discussed in:
https://reviews.llvm.org/D64101

Link: https://bugs.llvm.org/show_bug.cgi?id=42489
Link: https://groups.google.com/forum/#!topic/clang-built-linux/z-hRWP9KqPI

Reviewers: fhahn, hfinkel, efriedma

Reviewed By: fhahn, hfinkel, efriedma

Subscribers: efriedma, hiraditya, zzheng, dmgreen, llvm-commits, pirama, kees, nathanchance, E5ten, craig.topper, chandlerc, glider, void, srhines

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64368

llvm-svn: 366130
2019-07-15 21:16:29 +00:00
Matt Arsenault 0277249955 TableGen/GlobalISel: Fix handling of truncstore patterns
This was failing to import the AMDGPU truncstore patterns. The
truncating stores from 32-bit to 8/16 were then somehow being
incorrectly selected to a 4-byte store.

A separate check is emitted for the LLT size in comparison to the
specific memory VT, which looks strange to me but makes sense based on
the hierarchy of PatFrags used for the default truncstore PatFrags.

llvm-svn: 366129
2019-07-15 21:15:20 +00:00
Matt Arsenault d00d857801 TableGen: Add address space to matchers
Currently AMDGPU uses a CodePatPred to check address spaces from the
MachineMemOperand. Introduce a new first class property so that the
existing patterns can be easily modified to uses the new generated
predicate, which will also be handled for GlobalISel.

I would prefer these to match against the pointer type of the
instruction, but that would be difficult to get working with
SelectionDAG compatbility. This is much easier for now and will avoid
a painful tablegen rewrite for all the loads and stores.

I'm also not sure if there's a better way to encode multiple address
spaces in the table, rather than putting the number to expect.

llvm-svn: 366128
2019-07-15 20:59:42 +00:00
Bob Haarman 794346460a [clang] allow -fthinlto-index= without -x ir
Summary:
Previously, passing -fthinlto-index= to clang required that bitcode
files be explicitly marked by -x ir. This change makes us detect files
with object file extensions as bitcode files when -fthinlto-index= is
present, so that explicitly marking them is no longer necessary.
Explicitly specifying -x ir is still accepted and continues to be part
of the test case to ensure we continue to support it.

Reviewers: tejohnson, rnk, pcc

Subscribers: mehdi_amini, steven_wu, dexonsmith, arphaman, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D64610

llvm-svn: 366127
2019-07-15 20:51:44 +00:00
Julian Lettner 39d888c1e4 [TSan] Improve handling of stack pointer mangling in {set,long}jmp, pt.9
Switch over to computing the xor key in C, instead of assembly for
Linux/AArch64.

llvm-svn: 366126
2019-07-15 20:22:27 +00:00
Matt Arsenault 66ee934440 AMDGPU/GlobalISel: Allow scalar s1 and/or/xor
If a 1-bit value is in a 32-bit VGPR, the scalar opcodes set SCC to
whether the result is 0. If the inputs are SCC, these can be copied to
a 32-bit SGPR to produce an SCC result.

llvm-svn: 366125
2019-07-15 20:20:18 +00:00
Louis Dionne dfcd4384cb [libc++] Implement P0433: deduction guides for <unordered_map>
Thanks to Arthur O'Dwyer for the patch.

Differential Revision: https://reviews.llvm.org/D58590

llvm-svn: 366124
2019-07-15 20:06:01 +00:00
Evgeniy Stepanov c5e7f56249 ARM MTE stack sanitizer.
Add "memtag" sanitizer that detects and mitigates stack memory issues
using armv8.5 Memory Tagging Extension.

It is similar in principle to HWASan, which is a software implementation
of the same idea, but there are enough differencies to warrant a new
sanitizer type IMHO. It is also expected to have very different
performance properties.

The new sanitizer does not have a runtime library (it may grow one
later, along with a "debugging" mode). Similar to SafeStack and
StackProtector, the instrumentation pass (in a follow up change) will be
inserted in all cases, but will only affect functions marked with the
new sanitize_memtag attribute.

Reviewers: pcc, hctim, vitalybuka, ostannard

Subscribers: srhines, mehdi_amini, javed.absar, kristof.beyls, hiraditya, cryptoad, steven_wu, dexonsmith, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D64169

llvm-svn: 366123
2019-07-15 20:02:23 +00:00
Eric Fiselier c5d7b0c454 Constrain workaround to avoid affecting other buildbots
llvm-svn: 366122
2019-07-15 19:53:42 +00:00
Matt Arsenault c8291c94f8 AMDGPU/GlobalISel: Select G_AND/G_OR/G_XOR
llvm-svn: 366121
2019-07-15 19:50:07 +00:00
Matt Arsenault ad19b50c00 AMDGPU/GlobalISel: Don't constrain source register of VCC copies
This is a hack until I come up with a better way of dealing with the
pseudo-register banks used for boolean values. If the use instruction
constrains the register, the selector for the def instruction won't
see that the bank was VCC. A 1-bit SReg_32 is could ambiguously have
been SCCRegBank or VCCRegBank in wave32.

This is necessary to successfully select branches with and and/or/xor
condition.

llvm-svn: 366120
2019-07-15 19:48:36 +00:00
Matt Arsenault e1b52f4180 AMDGPU/GlobalISel: Fix selecting vcc->vcc bank copies
The extra test change is correct, although how it arrives there is a
bug that needs work. With wave32, the test for isVCC ambiguously
reports true for an SCC or VCC source. A new allocatable pseudo
register class for SCC may be necesssary.

llvm-svn: 366119
2019-07-15 19:46:48 +00:00
Matt Arsenault 3bfdb54d88 AMDGPU/GlobalISel: Fix not constraining result reg of copies to VCC
llvm-svn: 366118
2019-07-15 19:45:49 +00:00
Matt Arsenault 18b7133843 AMDGPU/GlobalISel: Fix handling of sgpr (not scc bank) s1 to VCC
This was emitting a copy from a 32-bit register to a 64-bit.

llvm-svn: 366117
2019-07-15 19:44:07 +00:00
Matt Arsenault 6ed315f89b AMDGPU/GlobalISel: Custom legalize G_INSERT_VECTOR_ELT
llvm-svn: 366116
2019-07-15 19:43:04 +00:00
Matt Arsenault b0e04c018c AMDGPU/GlobalISel: Custom legalize G_EXTRACT_VECTOR_ELT
Turn the constant cases into G_EXTRACTs.

llvm-svn: 366115
2019-07-15 19:40:59 +00:00
Matt Arsenault 5dfd466032 AMDGPU/GlobalISel: Fix G_ICMP for wave32
llvm-svn: 366114
2019-07-15 19:39:31 +00:00