Commit Graph

79 Commits

Author SHA1 Message Date
Andrew Trick dd79f0fcea misched: Use the TargetSchedModel interface wherever possible.
Allows the new machine model to be used for NumMicroOps and OutputLatency.

Allows the HazardRecognizer to be disabled along with itineraries.

llvm-svn: 165603
2012-10-10 05:43:09 +00:00
Andrew Trick 984d98bf6a misched: avoid scheduling an instruction twice.
llvm-svn: 165416
2012-10-08 18:53:53 +00:00
Andrew Trick a2733e9549 misched: add a hook for custom DAG postprocessing.
llvm-svn: 163915
2012-09-14 17:22:42 +00:00
Manman Ren 19f49ac624 Release build: guard dump functions with
"#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)"

No functional change. Update r163339.

llvm-svn: 163653
2012-09-11 22:23:19 +00:00
Andrew Trick 7a8e10042f Reorganize MachineScheduler interfaces and publish them in the header.
The Hexagon target decided to use a lot of functionality from the
target-independent scheduler. That's fine, and other targets should be
able to do the same. This reorg and API update makes that easy.

For the record, ScheduleDAGMI was not meant to be subclassed. Instead,
new scheduling algorithms should be able to implement
MachineSchedStrategy and be done. But if need be, it's nice to be
able to extend ScheduleDAGMI, so I also made that easier. The target
scheduler is somewhat more apt to break that way though.

llvm-svn: 163580
2012-09-11 00:39:15 +00:00
Manman Ren 742534c4dc Release build: guard dump functions with "ifndef NDEBUG"
No functional change.

llvm-svn: 163339
2012-09-06 19:06:06 +00:00
Andrew Trick ae53561b0c Simplify the computeOperandLatency API.
The logic for recomputing latency based on a ScheduleDAG edge was
shady. This bypasses the problem by requiring the client to provide
operand indices. This ensures consistent use of the machine model's
API.

llvm-svn: 162420
2012-08-23 00:39:43 +00:00
Craig Topper a538d831e6 Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
llvm-svn: 162347
2012-08-22 06:07:19 +00:00
Sylvestre Ledru 35521e2310 Fix a typo (the the => the)
llvm-svn: 160621
2012-07-23 08:51:15 +00:00
Andrew Trick 87255e340e I'm introducing a new machine model to simultaneously allow simple
subtarget CPU descriptions and support new features of
MachineScheduler.

MachineModel has three categories of data:
1) Basic properties for coarse grained instruction cost model.
2) Scheduler Read/Write resources for simple per-opcode and operand cost model (TBD).
3) Instruction itineraties for detailed per-cycle reservation tables.

These will all live side-by-side. Any subtarget can use any
combination of them. Instruction itineraries will not change in the
near term. In the long run, I expect them to only be relevant for
in-order VLIW machines that have complex contraints and require a
precise scheduling/bundling model. Once itineraries are only actively
used by VLIW-ish targets, they could be replaced by something more
appropriate for those targets.

This tablegen backend rewrite sets things up for introducing
MachineModel type #2: per opcode/operand cost model.

llvm-svn: 159891
2012-07-07 04:00:00 +00:00
Andrew Trick 2f26b34806 misched: allow NULL InstrItineraries.
llvm-svn: 159599
2012-07-02 21:55:12 +00:00
Andrew Trick 8c9e6728b3 misched: avoid scheduling instructions that can't be dispatched.
llvm-svn: 159408
2012-06-29 03:23:24 +00:00
Andrew Trick ce27bb999d misched: count micro-ops toward the issue limit.
llvm-svn: 159407
2012-06-29 03:23:22 +00:00
Benjamin Kramer b9f84bb0ce Guard private fields that are unused in Release builds with #ifndef NDEBUG.
llvm-svn: 158608
2012-06-16 21:48:13 +00:00
Andrew Trick 05ff4667eb Move RegisterClassInfo.h.
Allow targets to access this API. It's required for RegisterPressure.

llvm-svn: 158102
2012-06-06 20:29:31 +00:00
Andrew Trick 88517f608c Move RegisterPressure.h.
Make it a general utility for use by Targets.

llvm-svn: 158097
2012-06-06 19:47:35 +00:00
Andrew Trick 4544606c71 misched: API for minimum vs. expected latency.
Minimum latency determines per-cycle scheduling groups.
Expected latency determines critical path and cost.

llvm-svn: 158021
2012-06-05 21:11:27 +00:00
Andrew Trick d36adece50 misched: comments from code review.
llvm-svn: 157975
2012-06-05 03:44:26 +00:00
Andrew Trick 4e7f6a7702 misched: trace formatting
llvm-svn: 157455
2012-05-25 02:02:39 +00:00
Kaelyn Uhrain 85d8f0cba8 Silence unused variable warnings from when assertions are disabled.
llvm-svn: 157438
2012-05-24 23:37:49 +00:00
Andrew Trick a306a8a844 misched: Use the same scheduling heuristics with -misched-topdown/bottomup.
(except the part about choosing direction)

llvm-svn: 157437
2012-05-24 23:11:17 +00:00
Andrew Trick 79d3eecbb4 misched: Trace regpressure.
llvm-svn: 157429
2012-05-24 22:11:14 +00:00
Andrew Trick a8ad5f7c7b misched: Give each ReadyQ a unique ID
llvm-svn: 157428
2012-05-24 22:11:12 +00:00
Andrew Trick 61f1a278b8 misched: Added ScoreboardHazardRecognizer.
The Hazard checker implements in-order contraints, or interlocked
resources. Ready instructions with hazards do not enter the available
queue and are not visible to other heuristics.

The major code change is the addition of SchedBoundary to encapsulate
the state at the top or bottom of the schedule, including both a
pending and available queue.

The scheduler now counts cycles in sync with the hazard checker. These
are minimum cycle counts based on known hazards.

Targets with no itinerary (x86_64) currently remain at cycle 0. To fix
this, we need to provide some maximum issue width for all targets. We
also need to add the concept of expected latency vs. minimum latency.

llvm-svn: 157427
2012-05-24 22:11:09 +00:00
Andrew Trick ca47335461 misched: Release bottom roots in reverse order.
llvm-svn: 157426
2012-05-24 22:11:05 +00:00
Andrew Trick dd375dd34a misched: rename ReadyQ class
llvm-svn: 157425
2012-05-24 22:11:03 +00:00
Andrew Trick f378617773 misched: copy comments so compareRPDelta is readable by itself.
llvm-svn: 157424
2012-05-24 22:11:01 +00:00
Andrew Trick 6a50baa26e comments
llvm-svn: 157020
2012-05-17 22:37:09 +00:00
Andrew Trick 276a3e8c46 misched: trace ReadyQ.
llvm-svn: 157007
2012-05-17 18:35:13 +00:00
Andrew Trick 2202577d80 misched: Added 3-level regpressure back-off.
Introduce the basic strategy for register pressure scheduling.

1) Respect target limits at all times.

2) Indentify critical register classes (pressure sets).
   Track pressure within the scheduled region.
   Avoid increasing scheduled pressure for critical registers.

3) Avoid exceeding the max pressure of the region prior to scheduling.

Added logic for picking between the top and bottom ready Q's based on
regpressure heuristics.

Status: functional but needs to be asjusted to achieve good results.
llvm-svn: 157006
2012-05-17 18:35:10 +00:00
Andrew Trick 47a1feaea0 comment
llvm-svn: 157005
2012-05-17 18:35:07 +00:00
Andrew Trick 463b2f1f04 misched: fix liveness iterators
llvm-svn: 157003
2012-05-17 18:35:03 +00:00
Andrew Trick c5d7008f27 misched: Print machineinstrs with -debug-only=misched
llvm-svn: 156576
2012-05-10 21:06:21 +00:00
Andrew Trick 419eae2db7 misched: tracing register pressure heuristics.
llvm-svn: 156575
2012-05-10 21:06:19 +00:00
Andrew Trick 7ee9de51f2 misched: Add register pressure backoff to ConvergingScheduler.
Prioritize the instruction that comes closest to keeping pressure
under the target's limit. Then prioritize instructions that avoid
increasing the max pressure in the scheduled region. The max pressure
heuristic is a tad aggressive. Later I'll fix it to consider the
unscheduled pressure as well.

WIP: This is mostly functional but untested and not likely to do much good yet.
llvm-svn: 156574
2012-05-10 21:06:16 +00:00
Andrew Trick 795c1120a6 misched: Release only unscheduled nodes into ReadyQ.
llvm-svn: 156573
2012-05-10 21:06:14 +00:00
Andrew Trick 95dafd8b31 misched: Added ReadyQ container wrapper for Top and Bottom Queues.
llvm-svn: 156572
2012-05-10 21:06:12 +00:00
Andrew Trick 4add42f439 misched: Introducing Top and Bottom register pressure trackers during scheduling.
llvm-svn: 156571
2012-05-10 21:06:10 +00:00
Andrew Trick 4d4b5469ab Fix a naughty header include that breaks "installed" builds.
llvm-svn: 155486
2012-04-24 20:36:19 +00:00
Andrew Trick c3ea00565f misched: try (not too hard) to place debug values where they belong
llvm-svn: 155458
2012-04-24 18:04:37 +00:00
Andrew Trick cc45a28320 misched: ignore debug values during scheduling
llvm-svn: 155457
2012-04-24 18:04:34 +00:00
Andrew Trick 88639928bd misched: DAG builder support for tracking register pressure within the current scheduling region.
The DAG builder is a convenient place to do it. Hopefully this is more
efficient than a separate traversal over the same region.

llvm-svn: 155456
2012-04-24 17:56:43 +00:00
Andrew Trick 779b32a44e misched: Add finalizeScheduler to complete the target interface.
llvm-svn: 153827
2012-04-01 07:24:23 +00:00
Andrew Trick adb03b91ee misched: trace LiveIntervals after scheduling.
llvm-svn: 153161
2012-03-21 04:12:12 +00:00
Andrew Trick 54f7def703 misched: obvious iterator update fixes for bottom-up.
llvm-svn: 153160
2012-03-21 04:12:10 +00:00
Andrew Trick de670c0304 misched: cleanup main loop
llvm-svn: 153159
2012-03-21 04:12:07 +00:00
Lang Hames dd98c497b9 Add an option to the MI scheduler to cut off scheduling after a fixed number of
instructions have been scheduled. Handy for tracking down scheduler bugs, or
bugs exposed by scheduling.

llvm-svn: 153045
2012-03-19 18:38:38 +00:00
Benjamin Kramer 05e7a843aa Silence operator precedence warnings.
llvm-svn: 152711
2012-03-14 11:26:37 +00:00
Andrew Trick 8823decdd4 misched: implemented a framework for top-down or bottom-up scheduling.
New flags: -misched-topdown, -misched-bottomup. They can be used with
the default scheduler or with -misched=shuffle. Without either
topdown/bottomup flag -misched=shuffle now alternates scheduling
direction.

LiveIntervals update is unimplemented with bottom-up scheduling, so
only -misched-topdown currently works.

Capped the ScheduleDAG hierarchy with a concrete ScheduleDAGMI class.
ScheduleDAGMI is aware of the top and bottom of the unscheduled zone
within the current region. Scheduling policy can be plugged into
the ScheduleDAGMI driver by implementing MachineSchedStrategy.
ConvergingScheduler is now the default scheduling algorithm.
It exercises the new driver but still does no reordering.

llvm-svn: 152700
2012-03-14 04:00:41 +00:00
Andrew Trick 72515bef32 misched comments
llvm-svn: 152699
2012-03-14 04:00:38 +00:00