ee09394644
Register the MC object streamer.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140887
2011-09-30 21:29:38 +00:00
44220ca045
Register Asm backend. Add functions to MipsAsmBackend.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140886
2011-09-30 21:23:45 +00:00
587fe6cd52
Add MCELFObjectTargetWriter and MCAsmBackend classes.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140885
2011-09-30 21:04:02 +00:00
3bad73a900
Update CMake build.
...
llvm-svn: 140879
2011-09-30 20:44:33 +00:00
750ecec7d5
Initial implementation of MipsMCCodeEmitter.
...
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140878
2011-09-30 20:40:03 +00:00
011dafba61
Don't modify constant in-place.
...
llvm-svn: 140875
2011-09-30 19:58:46 +00:00
2f0cbf6a99
Tracing or debug-printing a newly formed instruction should not crash.
...
llvm-svn: 140874
2011-09-30 19:50:40 +00:00
ec4b6e7fe5
whitespace
...
llvm-svn: 140873
2011-09-30 19:48:58 +00:00
7ba8a8d656
Add definitions of Mips64 rotate instructions.
...
llvm-svn: 140870
2011-09-30 18:51:46 +00:00
24ff834671
float comparison to double 'zero' constant can just be a float 'zero.'
...
InstCombine was incorrectly considering the conversion of the constant
zero to be unsafe.
We want to transform:
define float @bar(float %x) nounwind readnone optsize ssp {
%conv = fpext float %x to double
%cmp = fcmp olt double %conv, 0.000000e+00
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
Into:
define float @bar(float %x) nounwind readnone optsize ssp {
%cmp = fcmp olt float %x, 0.000000e+00 ; <---- This
%conv1 = zext i1 %cmp to i32
%conv2 = sitofp i32 %conv1 to float
ret float %conv2
}
rdar://10215914
llvm-svn: 140869
2011-09-30 18:45:50 +00:00
e8e4dbf468
Constify 'isLSDA' and move a method out-of-line.
...
llvm-svn: 140868
2011-09-30 18:42:06 +00:00
129c52af18
Tidy up. Trailing whitespace.
...
llvm-svn: 140865
2011-09-30 18:09:53 +00:00
4e0dbee62b
ARM Darwin default relocation model is PIC.
...
This matches clang, so default options in llc and friends are now closer to
clang's defaults.
llvm-svn: 140863
2011-09-30 17:41:35 +00:00
9727af7657
isCommutable should be 0 for DSUBu.
...
llvm-svn: 140862
2011-09-30 17:26:36 +00:00
d2222c386c
ARM Fixup valus for movt/movw are for the whole value.
...
Remove an assert that was expecting only the relevant 16bit portion for
the fixup being handled. Also kill some dead code in the T2 portion.
rdar://9653509
llvm-svn: 140861
2011-09-30 17:23:05 +00:00
c874e2d8fb
Fix a bug in compare_numeric().
...
Thanks to Alexandru Dura and Jonas Paulsson for finding it.
llvm-svn: 140859
2011-09-30 17:03:55 +00:00
64b1aad4e3
MCJIT initialization TargetData
...
llvm-svn: 140856
2011-09-30 16:40:10 +00:00
ea3f90ae40
PTX: Various stylistic and code readability changes recommended by Jim Grosbach.
...
llvm-svn: 140855
2011-09-30 14:36:36 +00:00
957a6d5c51
PTX: Add programmable rounding mode specifier for int <-> fp conversion instrs.
...
Also take this opportunity to clean up the rounding mode pass.
llvm-svn: 140854
2011-09-30 13:46:52 +00:00
5c05579f94
Inlining often produces landingpad instructions with repeated
...
catch or repeated filter clauses. Teach instcombine a bunch
of tricks for simplifying landingpad clauses. Currently the
code only recognizes the GNU C++ and Ada personality functions,
but that doesn't stop it doing a bunch of "generic" transforms
which are hopefully fine for any real-world personality function.
If these "generic" transforms turn out not to be generic, they
can always be conditioned on the personality function. Probably
someone should add the ObjC++ personality function. I didn't as
I don't know anything about it.
llvm-svn: 140852
2011-09-30 13:12:16 +00:00
be5020eb95
Comment grammar fixes.
...
thanks to Duncan.
llvm-svn: 140850
2011-09-30 13:07:47 +00:00
3111d11f23
PTX: Attempt to cleanup/unify the handling of FP rounding modes. This requires
...
us to manually provide Pat<> definitions for all FP instruction patterns.
llvm-svn: 140849
2011-09-30 12:54:43 +00:00
319a1415b8
Instead of crashing when MCAsmInfo is NULL, add an assert.
...
This helps with porting code from 2.9 to 3.0 as TargetSelect.h changed location,
and if you include the old one by accident you will trigger this assert.
llvm-svn: 140848
2011-09-30 12:31:57 +00:00
61e256aa69
Mips64 shift instructions.
...
llvm-svn: 140841
2011-09-30 03:18:46 +00:00
7769a77710
Mips64 arithmetic and logical instructions with one source register and
...
immediate.
llvm-svn: 140839
2011-09-30 02:08:54 +00:00
efc761a1eb
ARM fix encoding of VMOV.f32 and VMOV.f64 immediates.
...
Encode the immediate into its 8-bit form as part of isel rather than later,
which simplifies things for mapping the encoding bits, allows the removal
of the custom disassembler decoding hook, makes the operand printer trivial,
and prepares things more cleanly for handling these in the asm parser.
rdar://10211428
llvm-svn: 140834
2011-09-30 00:50:06 +00:00
f2619ee3ff
Fill delay slot with useful instructions. Modified from Sparc's version of delay
...
slot filler.
Patch by Reed Kotler at Mips Technologies.
llvm-svn: 140825
2011-09-29 23:52:13 +00:00
69bc3de4fc
Create a machine basic block in the constant pool and retrieve the symbol for an MBB.
...
llvm-svn: 140824
2011-09-29 23:50:42 +00:00
a1127b2fa2
Support creating a constant pool value for a machine basic block.
...
This is used when we want to take the address of a machine basic block, but it's
not associated with a BB in LLVM IR.
llvm-svn: 140823
2011-09-29 23:48:44 +00:00
a3e7ffdae8
Fold two identical set lookups into one. No functionality change.
...
llvm-svn: 140821
2011-09-29 23:40:12 +00:00
4ac148dcbc
When eliminating unnecessary retain+autorelease on return values,
...
handle the case where the retain is in a different basic block.
rdar://10210274.
llvm-svn: 140815
2011-09-29 22:27:34 +00:00
2053a5dd64
Don't eliminate objc_retainBlock calls on stack objects if the
...
objc_retainBlock call is potentially responsible for copying
the block to the heap to extend its lifetime. rdar://10209613.
llvm-svn: 140814
2011-09-29 22:25:23 +00:00
36036412e2
Mips64 arithmetic and logical instructions with two source registers.
...
llvm-svn: 140806
2011-09-29 20:37:56 +00:00
95031ed837
Clean up uses of switch instructions so they are not dependent on the operand ordering. Patch by Stepan Dyatkovskiy.
...
llvm-svn: 140803
2011-09-29 20:21:17 +00:00
a9e8a2504c
Cosmetic changes, as per Nick's review.
...
llvm-svn: 140785
2011-09-29 16:46:47 +00:00
cac86805bf
Place this bracket according to the LLVM style.
...
llvm-svn: 140784
2011-09-29 16:01:46 +00:00
abcc57669d
PTX: Fix broken shared library build
...
llvm-svn: 140783
2011-09-29 14:25:48 +00:00
dd1904e7a6
Expand the x86 V_SET0* pseudos right after register allocation.
...
This also makes it possible to reduce the number of pseudo instructions
and get rid of the encoding information.
llvm-svn: 140776
2011-09-29 05:10:54 +00:00
15b3c9c684
Target/ARM: Unbreak! CMake! Build!
...
llvm-svn: 140774
2011-09-29 03:32:49 +00:00
bf64024a39
Delete NEONMoveFix, now unused.
...
llvm-svn: 140773
2011-09-29 02:56:45 +00:00
f7ad189033
Use ExecutionDepsFix instead of NEONMoveFix.
...
This enables NEON domain tracking across basic blocks, but should
otherwise do the same thing.
llvm-svn: 140772
2011-09-29 02:48:41 +00:00
168dfffdb8
typo + pasto
...
llvm-svn: 140769
2011-09-29 01:53:08 +00:00
463b05a2d0
Remove NumImplicitOps which is now unused.
...
llvm-svn: 140767
2011-09-29 01:47:36 +00:00
bc6de90a5f
LSR: rewrite inner loops only.
...
Rewriting the entire loop nest now requires -enable-lsr-nested.
See PR11035 for some performance data.
A few unit tests specifically test nested LSR, and are now under a flag.
llvm-svn: 140762
2011-09-29 01:33:38 +00:00
a0d5f268a9
Move to ISelLowering.
...
llvm-svn: 140754
2011-09-29 01:13:55 +00:00
fd47d8af8b
PTX: Add new patterns for bitconvert and any_extend
...
llvm-svn: 140753
2011-09-29 01:13:12 +00:00
d299dccf91
Use the local we already set up.
...
llvm-svn: 140745
2011-09-29 00:50:59 +00:00
2318d1e0e9
Rewrite MachineInstr::addOperand() to avoid NumImplicitOps.
...
The function needs to scan the implicit operands anyway, so no
performance is won by caching the number of implicit operands added to
an instruction.
This also fixes a bug when adding operands after an implicit operand has
been added manually. The NumImplicitOps count wasn't kept up to date.
MachineInstr::addOperand() will now consistently place all explicit
operands before all the implicit operands, regardless of the order they
are added. It is possible to change an MI opcode and add additional
explicit operands. They will be inserted before any existing implicit
operands.
The only exception is inline asm instructions where operands are never
reordered. This is because of a hack that marks explicit clobber regs
on inline asm as <implicit-def> to please the fast register allocator.
This hack can go away when InstrEmitter and FastIsel can add exact
<dead> flags to physreg defs.
llvm-svn: 140744
2011-09-29 00:40:51 +00:00
6728958279
Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
...
It broke the unit tests. Please reapply with tests fixed.
llvm-svn: 140735
2011-09-28 23:59:28 +00:00
8156376aa9
Tighten a ARM dag combine condition to avoid an identity transformation, which
...
ends up introducing a cycle in the DAG.
rdar://10196296
llvm-svn: 140733
2011-09-28 23:16:31 +00:00
5a1b4a80c3
Define classes for unary and binary FP instructions and use them to define
...
multiclasses.
llvm-svn: 140731
2011-09-28 21:58:01 +00:00
899da52d60
Have the SjLjEHPrepare pass do some more heavy lifting.
...
Upon further review, most of the EH code should remain written at the IR
level. The part which breaks SSA form is the dispatch table, so that part will
be moved to the back-end.
llvm-svn: 140730
2011-09-28 21:56:53 +00:00
2fb357a5b0
PR11033: Make sure we don't generate PCMPGTQ and PCMPEQQ if the target CPU does not support them.
...
llvm-svn: 140723
2011-09-28 21:00:25 +00:00
800619f2bb
Object: Add isSection{Data,BSS}.
...
llvm-svn: 140721
2011-09-28 20:57:30 +00:00
315b9573c6
Perform the lowering only if there are invokes.
...
llvm-svn: 140719
2011-09-28 20:29:45 +00:00
dfe5acd34e
Ahem...actually *add* the ARMSjLjLowering pass to the pass manager.
...
llvm-svn: 140718
2011-09-28 20:29:28 +00:00
933d51682f
PTX: Fix alignment logic
...
llvm-svn: 140709
2011-09-28 18:24:58 +00:00
6f37b4a5a5
Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.
...
llvm-svn: 140705
2011-09-28 18:11:19 +00:00
edc172d4cc
Remove definitions of branch-on-FP-likely instructions. They are deprecated.
...
llvm-svn: 140704
2011-09-28 17:56:55 +00:00
c117967b19
Mips64 predicate definitions. Patch by Liu.
...
llvm-svn: 140703
2011-09-28 17:50:27 +00:00
ef8e4efff8
indvars: generalize SCEV getPreStartForSignExtend.
...
Handle general Add expressions to avoid leaving around redundant
32-bit IVs.
llvm-svn: 140701
2011-09-28 17:02:54 +00:00
f3d1d4eb4b
PTX: MC-ize the PTX backend (patch 2 of N)
...
Get rid of some of the no-longer-needed parts of PTXAsmPrinter.
llvm-svn: 140698
2011-09-28 14:32:06 +00:00
5e18b14ee2
PTX: MC-ize the PTX back-end (patch 1 of N)
...
Lay some groundwork for converting to MC-based asm printer. This is the first
of probably many patches to bring the back-end back up-to-date with all of the
recent MC changes.
llvm-svn: 140697
2011-09-28 14:32:04 +00:00
21efa7d6e1
Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit.
...
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.
Add decoder and disassembler tests.
Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.
llvm-svn: 140696
2011-09-28 14:21:38 +00:00
2e67937f76
A typeid of zero means a cleanup, not a catch. This case occurs
...
when there is both a catch and a cleanup. Correct the comment.
llvm-svn: 140686
2011-09-28 09:13:02 +00:00
8747e3e7ea
PTX: Simplify code. No functionality change.
...
llvm-svn: 140680
2011-09-28 04:32:36 +00:00
5d7a73fa8c
PTX: Pass param name strings per const reference.
...
The copies caused use-after-free bugs on std::string implementations without COW (i.e. anything but libstdc++)
llvm-svn: 140679
2011-09-28 04:08:02 +00:00
baf3941fde
Strip off pointer casts when looking at the eh.sjlj.functioncontext's argument.
...
llvm-svn: 140678
2011-09-28 03:52:41 +00:00
225e8481b0
Bitcast the alloca to an i8* to match the intrinsic's signature.
...
llvm-svn: 140677
2011-09-28 03:47:11 +00:00
66b110f571
Create and use an llvm.eh.sjlj.functioncontext intrinsic.
...
This intrinsic is used to pass the index of the function context to the back-end
for further processing. The back-end is in charge of filling in the rest of the
entries.
llvm-svn: 140676
2011-09-28 03:36:43 +00:00
2e76ca9d9a
In the new EH model, setup the function context and the call site info.
...
The DWARF exception pass uses the call site information, which is set up here. A
pre-RA pass is too late for it to use this information. So create and setup the
function context here, and then insert the call site values here (and map the
call sites for the DWARF EH pass). This is simpler than the original pass, and
doesn't make the CFG lose its SSA-ness.
It's a win-win-win-win-lose-win-win situation.
llvm-svn: 140675
2011-09-28 03:14:05 +00:00
e6138e3ad1
Don't conditionalize execution of the SjLj EH prepare pass.
...
We may need an SjLj EH preparation pass for some call site information, at least
in the short term.
llvm-svn: 140674
2011-09-28 03:07:34 +00:00
e0e30532a5
indvars should hoist [sz]ext because licm is not rerun.
...
llvm-svn: 140670
2011-09-28 01:35:36 +00:00
5f476dc3ef
PR10628: Fix getModRefInfo so it queries the underlying alias() implementation correctly while checking nocapture calls.
...
llvm-svn: 140666
2011-09-28 00:34:27 +00:00
bd5109f14d
Rename class and clean up source.
...
No functional change intended.
llvm-svn: 140664
2011-09-28 00:01:56 +00:00
934b7d7645
Rename SSEDomainFix -> lib/CodeGen/ExecutionDepsFix.
...
I'll clean up the source in the next commit.
llvm-svn: 140663
2011-09-28 00:01:54 +00:00
ae40dc735d
Remove MipsFPRound. Mips1 is no longer supported.
...
llvm-svn: 140661
2011-09-27 23:55:37 +00:00
30c811246f
Remove X86-dependent stuff from SSEDomainFix.
...
This also enables domain swizzling for AVX code which required a few
trivial test changes.
The pass will be moved to lib/CodeGen shortly.
llvm-svn: 140659
2011-09-27 23:50:46 +00:00
e3e36f80f5
Unbreak CMake build.
...
llvm-svn: 140655
2011-09-27 23:29:59 +00:00
f9b71a2e01
Implement TII::get/setExecutionDomain() for ARM.
...
llvm-svn: 140653
2011-09-27 22:57:21 +00:00
b48c994cc0
Promote the X86 Get/SetSSEDomain functions to TargetInstrInfo.
...
I am going to unify the SSEDomainFix and NEONMoveFix passes into a
single target independent pass. They are essentially doing the same
thing.
llvm-svn: 140652
2011-09-27 22:57:18 +00:00
c63af1b7b6
ARM Thumb2 asm parsing [SU]XT[BH] without rotate but with .w.
...
Add inst alias to handle these assembly forms. Add tests, too.
rdar://10178799
llvm-svn: 140647
2011-09-27 22:18:54 +00:00
354ff9e348
This is the start of the new SjLj EH preparation pass, which will replace the
...
current IR-level pass.
The old SjLj EH pass has some problems, especially with the new EH model. Most
significantly, it violates some of the new restrictions the new model has. For
instance, the 'dispatch' table wants to jump to the landing pad, but we cannot
allow that because only an invoke's unwind edge can jump to a landing pad. This
requires us to mangle the code something awful. In addition, we need to keep the
now dead landingpad instructions around instead of CSE'ing them because the
DWARF emitter uses that information (they are dead because no control flow edge
will execute them - the control flow edge from an invoke's unwind is superceded
by the edge coming from the dispatch).
Basically, this pass belongs not at the IR level where SSA is king, but at the
code-gen level, where we have more flexibility.
llvm-svn: 140646
2011-09-27 22:14:12 +00:00
a5d18f2d7e
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
...
of the instruction definitions using Pat<>.
llvm-svn: 140644
2011-09-27 22:01:01 +00:00
7a6e8f2c5d
Remove an invalid assert that is really just asserting when the scheduler emits
...
a suboptimal schedule.
llvm-svn: 140643
2011-09-27 21:59:16 +00:00
af136f71ec
Rename AddSelectionDAGCSEId() to addSelectionDAGCSEId().
...
Naming conventions consistency. No functional change.
llvm-svn: 140636
2011-09-27 20:59:33 +00:00
547b6c5ecd
Stop emitting instructions with the name "tmp" they eat up memory and have to be uniqued, without any benefit.
...
If someone prefers %tmp42 to %42, run instnamer.
llvm-svn: 140634
2011-09-27 20:39:19 +00:00
bf415251df
These symbols appear to be visible by SearchForAddressOfSymbol and no longer
...
require special case handling.
rdar://10117377
llvm-svn: 140629
2011-09-27 20:01:41 +00:00
d3b7b12618
Object: Add archive support.
...
llvm-svn: 140626
2011-09-27 19:36:55 +00:00
68ba81346e
Check that catch clauses have pointer type.
...
llvm-svn: 140625
2011-09-27 19:34:22 +00:00
4f7054e56e
PTX: Fix case where printed alignment could be 0
...
llvm-svn: 140624
2011-09-27 19:25:49 +00:00
e074593498
PTX: Use external symbols to keep track of params and locals. This also fixes
...
a couple of outstanding issues with frame objects occuring as instruction
operands.
llvm-svn: 140616
2011-09-27 18:12:55 +00:00
1c7597693c
Use existing function.
...
llvm-svn: 140615
2011-09-27 17:55:08 +00:00
e41b1d59f0
Fix function MipsRegisterInfo::getRegisterNumbering.
...
Return numbers of 64-bit registers.
llvm-svn: 140609
2011-09-27 17:15:27 +00:00
ff5d0965b0
Do not add the pass that restores $gp if target is Mips64.
...
llvm-svn: 140607
2011-09-27 16:58:43 +00:00
86de1a666d
Have the verifier check that all landingpad operands are constants.
...
llvm-svn: 140606
2011-09-27 16:43:19 +00:00
38b3b83362
Cleanup PromoteIntOp_EXTRACT_VECTOR_ELT and PromoteIntRes_SETCC.
...
Add a new method: getAnyExtOrTrunc and use it to replace the manual check.
llvm-svn: 140603
2011-09-27 11:16:47 +00:00
1b857d2762
Revert r140463; The patch assumes that <4 x i1> is saved to memory as 4 x i8,
...
while the decision is to bit-pack small values.
llvm-svn: 140601
2011-09-27 10:48:29 +00:00
bb050745e7
Mark MipsPseudo isPseudo.
...
llvm-svn: 140598
2011-09-27 04:57:54 +00:00
9f01f89386
PTX: Add support for sitofp in backend
...
llvm-svn: 140593
2011-09-27 01:04:47 +00:00
90f90da156
Split the landing pad basic block with the correct function. Also merge the
...
split landingpad instructions into a PHI node.
PR11016
llvm-svn: 140592
2011-09-27 00:59:31 +00:00
581243919d
Disable LSR retry by default.
...
Disabling aggressive LSR saves compilation time, and with the new
indvars behavior usually improves performance.
llvm-svn: 140590
2011-09-27 00:44:14 +00:00
8868faec63
LSR, one of the new Cost::isLoser() checks did not get merged in the previous checkin.
...
llvm-svn: 140583
2011-09-26 23:35:25 +00:00
b1a9f65487
Remove extraneous commit garbage.
...
llvm-svn: 140581
2011-09-26 23:14:02 +00:00
784729d408
LSR cost metric minor fix and verification.
...
The minor bug heuristic was noticed by inspection. I added the
isLoser/isValid helpers because they will become more
important with subsequent checkins.
llvm-svn: 140580
2011-09-26 23:11:04 +00:00
a6a9c20c23
Set register class of a register according to value of HasMips64.
...
llvm-svn: 140570
2011-09-26 21:55:17 +00:00
7b502920ef
Define variable HasMips64 in MipsTargetLowering.
...
llvm-svn: 140569
2011-09-26 21:47:02 +00:00
e5ce709022
In single float mode, double precision FP arguments are passed in integer
...
registers, so there is no need to check here.
llvm-svn: 140568
2011-09-26 21:37:50 +00:00
f01e2de5e6
ASR #32 is not allowed on Thumb2 USAT and SSAT instructions.
...
llvm-svn: 140560
2011-09-26 21:06:22 +00:00
5c91891cf3
Enhance alias analysis for atomic instructions a bit. Upgrade a couple alias-analysis tests to the new atomic instructions.
...
llvm-svn: 140557
2011-09-26 20:15:28 +00:00
da2919dbd8
PTX: Fix memcpy intrinsic to handle 64-bit pointers
...
llvm-svn: 140556
2011-09-26 19:19:48 +00:00
b40da7f956
PTX: Implement PTXSelectionDAGInfo
...
llvm-svn: 140549
2011-09-26 18:57:27 +00:00
c3edaddfea
PTX: Implement ISD::ANY_EXTEND
...
llvm-svn: 140548
2011-09-26 18:57:24 +00:00
1395cf8423
PTX: Fix detection of stack load/store vs. global load/store, as well as fix the
...
printing of local offsets
llvm-svn: 140547
2011-09-26 18:57:22 +00:00
0ceb8cadd2
Fix emission of debug data for global variables. getContext() on DIGlobalVariables is not valid any more.
...
llvm-svn: 140539
2011-09-26 17:40:42 +00:00
f8dd701bf9
PTX: SM > 2.0 implies +double
...
llvm-svn: 140536
2011-09-26 16:20:36 +00:00
14defde057
PTX: Fix some lingering issues with stack allocation
...
llvm-svn: 140535
2011-09-26 16:20:34 +00:00
37fd87675f
PTX: Split up the TableGen instruction definitions into logical units
...
llvm-svn: 140534
2011-09-26 16:20:31 +00:00
d40f5ababf
PTX: Unify handling of loads/stores
...
llvm-svn: 140533
2011-09-26 16:20:28 +00:00
8c80019352
PTX: Handle FrameIndex nodes
...
llvm-svn: 140532
2011-09-26 16:20:25 +00:00
b1fbf9ff26
PR11004: Inline memcpy to avoid generating nested call sequence. Un-XFAIL 2011-06-09-TailCallByVal and 2010-11-04-BigByval
...
llvm-svn: 140516
2011-09-26 06:13:20 +00:00
45faba98b4
Fix VEX decoding in i386 mode. Fixes PR11008.
...
llvm-svn: 140515
2011-09-26 05:12:43 +00:00
df977fedb6
Add target hook for pseudo instruction expansion.
...
Many targets use pseudo instructions to help register allocation. Like
the COPY instruction, these pseudos can be expanded after register
allocation. The early expansion can make life easier for PEI and the
post-ra scheduler.
This patch adds a hook that is called for all remaining pseudo
instructions from the ExpandPostRAPseudos pass.
llvm-svn: 140472
2011-09-25 19:21:35 +00:00
2279949129
[vector-select] Address one of the issues in pr10902. EXTRACT_VECTOR_ELEMENT
...
SDNodes may return values which are wider than the incoming element types. In
this patch we fix the integer promotion of these nodes.
Fixes spill-q.ll when running -promote-elements.
llvm-svn: 140471
2011-09-25 18:59:42 +00:00
fd719d184e
Clean up code after renaming LowerSubregs -> ExpandPostRAPseudos.
...
No functional change intended.
llvm-svn: 140470
2011-09-25 16:46:08 +00:00
f152df1e6b
Rename LowerSubregs to ExpandPostRAPseudos.
...
I'll fix the file contents in the next commit.
This pass is currently expanding the COPY and SUBREG_TO_REG pseudos. I
am going to add a hook so targets can expand more pseudo-instructions
after register allocation.
Many targets have pseudo-instructions that assist the register
allocator. They can be expanded after register allocation, before PEI
and PostRA scheduling.
llvm-svn: 140469
2011-09-25 16:46:00 +00:00
f550fa9173
Sort CMakeLists.txt.
...
llvm-svn: 140465
2011-09-24 22:06:35 +00:00
c2deabd202
Implement Duncan's suggestion to use the result of getSetCCResultType if it is legal
...
(this is always the case for scalars), otherwise use the promoted result type.
Fix test/CodeGen/X86/vsplit-and.ll when promote-elements is enabled.
llvm-svn: 140464
2011-09-24 19:48:19 +00:00
77426a754b
[Vector-Select] Address one of the problems in 10902.
...
When generating the trunc-store of i1's, we need to use the vector type and not
the scalar type.
This patch fixes the assertion in CodeGen/Generic/bool-vector.ll when
running with -promote-elements.
llvm-svn: 140463
2011-09-24 18:32:19 +00:00
7d7ee0c3ac
Add .td file.
...
llvm-svn: 140446
2011-09-24 01:40:18 +00:00
e96273e75d
Preparation for adding simple Mips64 instructions.
...
llvm-svn: 140443
2011-09-24 01:34:44 +00:00
55cf2ed148
Only run MF.verify() with EXPENSIVE_CHECKS=1.
...
llvm-svn: 140441
2011-09-24 01:11:19 +00:00
9b92e2be30
sys::Process: Add a SetWorkingDirectory method.
...
llvm-svn: 140433
2011-09-23 23:23:36 +00:00
8b2fe2f744
LSR minor bug fix in RateRegister.
...
No test case. Noticed by inspection and I doubt it ever affects the
outcome of the overall heuristic, let alone final codegen.
llvm-svn: 140431
2011-09-23 23:05:19 +00:00
3bb99bc957
Verify that terminators follow non-terminators.
...
This exposes a -segmented-stacks bug.
llvm-svn: 140429
2011-09-23 22:45:39 +00:00
8a15a5aa93
PR10998: It is not legal to sink an instruction past the terminator of a block; make sure we don't do that.
...
llvm-svn: 140428
2011-09-23 22:41:57 +00:00
4916840eb8
Teach the Thumb2 AsmParser to accept pre-indexed loads/stores with an offset of #-0.
...
llvm-svn: 140426
2011-09-23 22:25:02 +00:00
2056d15bd9
Also match negative offsets for addrmode3 and addrmode5.
...
Math is hard, and isScaledConstantInRange() always returned false for
negative constants. It was doing unsigned division of negative numbers
before casting back to signed.
llvm-svn: 140425
2011-09-23 22:10:33 +00:00
b0b865d658
Add more fixed bits to USAT16 encoding to filter out incorrect decodings.
...
llvm-svn: 140422
2011-09-23 21:57:50 +00:00
737beaf86d
Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions.
...
llvm-svn: 140420
2011-09-23 21:26:40 +00:00
987a878946
Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated.
...
llvm-svn: 140415
2011-09-23 21:07:25 +00:00
ffa8428acf
Revert r140412. This affects more instructions than intended.
...
llvm-svn: 140413
2011-09-23 21:02:01 +00:00
7591d0c363
Thumb2 register-shifted-register loads cannot target the PC or the SP.
...
llvm-svn: 140412
2011-09-23 21:00:32 +00:00
d6af2c62b4
Implement N32/64 calling convention. Patch by Liu.
...
llvm-svn: 140401
2011-09-23 19:08:15 +00:00
ceb55e72de
Make FGR64RegisterClass available if target is Mips64.
...
llvm-svn: 140397
2011-09-23 18:28:39 +00:00
77709a6793
Add definitions of 64-bit register files. Add code for returning Mips64's sets of
...
callee-saved registers and reserved registers.
llvm-svn: 140395
2011-09-23 18:11:56 +00:00
71d32c980d
PTX: Fix parameter order bug
...
llvm-svn: 140394
2011-09-23 17:59:11 +00:00
24e45cabbc
Fix a couple of 80 column violations.
...
patch contributed by Jia Liu!
llvm-svn: 140391
2011-09-23 17:24:41 +00:00
6e84a68023
PTX: Cleanup unused code in PTXMachineFunctionInfo
...
llvm-svn: 140390
2011-09-23 17:15:53 +00:00
0f1af22183
PTX: Fix another 80-column violation
...
llvm-svn: 140387
2011-09-23 16:50:35 +00:00
37f35f0083
PTX: Handle function call return values
...
llvm-svn: 140386
2011-09-23 16:48:41 +00:00
ae191ef63b
Fix 80 column violations.
...
Original patch by Liu.
llvm-svn: 140385
2011-09-23 16:28:10 +00:00
a54fd541c2
Implement Chris's suggestion of legalizing the various SSE and AVX
...
hadd/hsub intrinsics into the new fhadd/fhsub X86 node.
llvm-svn: 140383
2011-09-23 16:10:22 +00:00
6c23d2ee55
PTX: Start fixing function calls
...
llvm-svn: 140378
2011-09-23 14:31:12 +00:00
edc6bf474d
PTX: Remove PTX calling convention files
...
llvm-svn: 140377
2011-09-23 14:18:27 +00:00
f2b540e815
[PATCH 2/2] PTXInstrInfo.td PTXIntrinsicInstrInfo.td 80 columns
...
From 5936c03172e251f12a0332d1033de5718e6e2091 Mon Sep 17 00:00:00 2001
---
lib/Target/PTX/PTXInstrInfo.td | 165 ++++++++++++++++++++----------
lib/Target/PTX/PTXIntrinsicInstrInfo.td | 88 +++++++++++------
2 files changed, 167 insertions(+), 86 deletions(-)
llvm-svn: 140376
2011-09-23 14:18:24 +00:00
b823e41bf4
PTX: Generalize handling of .param types
...
llvm-svn: 140375
2011-09-23 14:18:22 +00:00
2f82cc61af
PTX: Cleanup unused code in the PTXMFInfoExtract pass
...
llvm-svn: 140374
2011-09-23 14:18:19 +00:00
b461176cfb
Tweak the handling of MERGE_VALUES nodes: remove the need for
...
DecomposeMERGE_VALUES to "know" that results are legalized in
a particular order, by passing it the number of the result
being legalized (the type legalization core provides this, it
just needs to be passed on).
llvm-svn: 140373
2011-09-23 13:59:22 +00:00
57e30726ad
Vector-Select: Address one of the problems in pr10902. Add handling for the
...
integer-promotion of CONCAT_VECTORS.
Test: test/CodeGen/X86/widen_shuffle-1.ll
This patch fixes the above tests (when running in with -promote-elements).
llvm-svn: 140372
2011-09-23 09:33:24 +00:00
42fe6bd5f2
Add definitions of 64-bit int registers.
...
llvm-svn: 140366
2011-09-23 02:33:15 +00:00
61bbcce84a
Do not rely on the enum values of argument registers A0-A3 being consecutive.
...
Define function getNextIntArgReg, which takes a register as a parameter and
returns the next O32 argument integer register. Use this function when double
precision floating point arguments are passed in two integer registers.
llvm-svn: 140363
2011-09-23 00:58:33 +00:00
64a4bf1788
PR10989: Don't print .hidden on Windows.
...
llvm-svn: 140356
2011-09-23 00:13:02 +00:00
87c844cdf8
PR10991: make fast-isel correctly check whether accessing a global through an alias involves thread-local storage. (I'm not entirely sure how this is supposed to work, but this patch makes fast-isel consistent with the normal isel path.)
...
llvm-svn: 140355
2011-09-22 23:41:28 +00:00
f25c37e384
Make changes in instruction and pattern definitions so that tablegen does not
...
complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
adea3f0c01
Add new files to CMake.
...
llvm-svn: 140352
2011-09-22 23:20:48 +00:00
e83e1b2d2c
Fix SimplifySelectCC to add newly created nodes to the DAGCombiner
...
worklist, as it may be possible to perform further optimization on them.
llvm-svn: 140349
2011-09-22 23:01:29 +00:00
f05864ad7d
Add support for GR32 <-> FR32 cross class copies.
...
We already support GR64 <-> VR128 copies. All of these copies break
partial register dependencies by zeroing the high part of the target
register.
llvm-svn: 140348
2011-09-22 22:45:24 +00:00
fbf0fba9f4
Update CMake build.
...
llvm-svn: 140347
2011-09-22 22:38:34 +00:00
6cca67fc4a
Start stubbing out MCModule and MCAtom, which provide an API for accessing the rich disassembly of a complete object or executable.
...
These are very much a work in progress, and not really useful yet.
llvm-svn: 140345
2011-09-22 22:32:22 +00:00
e92e5ee81f
Constrain register classes instead of emitting copies.
...
Sometimes register class constraints are trivial, like GR32->GR32_NOSP,
or GPR->rGPR. Teach InstrEmitter to simply constrain the virtual
register instead of emitting a copy in these cases.
Normally, these copies are handled by the coalescer. This saves some
coalescer work.
llvm-svn: 140340
2011-09-22 21:39:34 +00:00
0f36544c08
Add a MinNumRegs argument to MRI::constrainRegClass().
...
The function will refuse to use a register class with fewer registers
than MinNumRegs. This can be used by clients to avoid accidentally
increase register pressure too much.
The default value of MinNumRegs=0 doesn't affect how constrainRegClass()
works.
llvm-svn: 140339
2011-09-22 21:39:31 +00:00
0e4fcb8e3b
Synthesize SSE3/AVX 128 bit horizontal add/sub instructions from
...
floating point add/sub of appropriate shuffle vectors. Does not
synthesize the 256 bit AVX versions because they work differently.
llvm-svn: 140332
2011-09-22 20:15:48 +00:00
f9b785f185
PR10987: add a missed safety check to isSafePHIToSpeculate in scalarrepl.
...
llvm-svn: 140327
2011-09-22 18:56:30 +00:00
56acf840f1
Print parentheses in next line.
...
llvm-svn: 140325
2011-09-22 18:29:29 +00:00
c021a4b8b4
Change subreg index of AFPR64 from sub_fpeven to sub_32 per Jakob's comment.
...
llvm-svn: 140324
2011-09-22 18:24:21 +00:00
79a45a839c
Define a new sub-register index sub_32 for accessing the 32-bit sub-register of
...
a 64-bit integer register. Move the subreg index definitions to the beginning
of the file.
llvm-svn: 140319
2011-09-22 17:57:32 +00:00
a58fde665a
Use the C personality function instead of the C++ personality function.
...
llvm-svn: 140318
2011-09-22 17:56:40 +00:00
35b7fe8c25
Print three closing parentheses when Kind is either VK_Mips_GPOFF_HI or
...
VK_Mips_GPOFF_LO.
llvm-svn: 140316
2011-09-22 17:44:37 +00:00
da33066424
Add F31 to the set of callee-saved registers.
...
llvm-svn: 140315
2011-09-22 17:35:03 +00:00
cf9c4f80ba
Fix typo.
...
llvm-svn: 140313
2011-09-22 17:26:58 +00:00
efc211d977
PTX: Remove physical register defs
...
llvm-svn: 140310
2011-09-22 16:45:48 +00:00
43787cd447
PTX: Use .param space for device function return values on SM 2.0+, and attempt
...
to fix up parameter passing on SM < 2.0
llvm-svn: 140309
2011-09-22 16:45:46 +00:00
ae10a30386
PTX: Fix style issues
...
llvm-svn: 140308
2011-09-22 16:45:43 +00:00
8bc34e72e9
PTX: Fixup codegen to handle emission of virtual registers.
...
llvm-svn: 140307
2011-09-22 16:45:40 +00:00
47423e4fb9
PTX: Customize codegen passes in backend
...
llvm-svn: 140306
2011-09-22 16:45:37 +00:00
28a548ebe3
PTX: Add new PTX-specific register allocator that keeps virtual registers
...
instead of allocating physical registers.
This is part of a work-in-progress overhaul of the PTX register allocation scheme.
llvm-svn: 140305
2011-09-22 16:45:33 +00:00
6d1872b77a
Fix register printing in disassembling of push/pop of segment registers and in/out in Intel syntax mode. Fixes PR10960
...
llvm-svn: 140299
2011-09-22 07:01:50 +00:00
3d10b95bf7
Add definition of 64-bit floating registers used for Mips64.
...
llvm-svn: 140297
2011-09-22 03:48:47 +00:00
cfd26cd744
The SSE version differences for fmin/fmax are more involved than I thought.
...
- x87: no min or max.
- SSE1: min/max for single precision scalars and vectors.
- SSE2: min/max for single and double precision scalars and vectors.
- AVX: as SSE2, but also supports the wider ymm vectors. (this is covered by the isTypeLegal check)
llvm-svn: 140296
2011-09-22 03:27:22 +00:00
25ce3647e5
Add enums and functions for symbols Mips64 uses.
...
llvm-svn: 140295
2011-09-22 03:09:07 +00:00
dc397a6402
X86: Don't form min/max nodes if the target is missing SSE.
...
llvm-svn: 140294
2011-09-22 03:01:42 +00:00
dc7baed9d3
Mips64 aligns stack on 16-byte boundary.
...
llvm-svn: 140292
2011-09-22 02:53:37 +00:00
6a5f8b2fd4
Remove unnecessary condition check.
...
llvm-svn: 140291
2011-09-22 02:41:29 +00:00
fbe52c0192
Turns out that Thumb2 ADR doesn't need special printing like LDR does. Fix other test failures I caused.
...
llvm-svn: 140284
2011-09-21 23:53:44 +00:00
f52c68f0ca
Print out immediate offset versions of PC-relative load/store instructions as [pc, #123 ] rather than simply #123 .
...
llvm-svn: 140283
2011-09-21 23:44:46 +00:00
5e6b65cf0d
Do not unnecessarily use AT_specification DIE because it does not add any value.
...
Few weeks ago, llvm completely inverted the debug info graph. Earlier each debug info node used to keep track of its compile unit, now compile unit keeps track of important nodes. One impact of this change is that the global variable's do not have any context, which should be checked before deciding to use AT_specification DIE.
llvm-svn: 140282
2011-09-21 23:41:11 +00:00
ef65f002df
Fix for DbgInfoPrinter.cpp:174:12: warning: ‘LineNo’ may be used uninitialized in this function.
...
llvm-svn: 140281
2011-09-21 23:34:23 +00:00
f4bbc0416f
The last verification check for the new EH model.
...
This makes sure that the unwind destination of an invoke is a landing pad.
llvm-svn: 140280
2011-09-21 22:57:02 +00:00
7b3fc8ee38
Attempt to update the shadow stack GC pass to the new EH model.
...
This inserts a cleanup landingpad instruction and a resume to mimic the old
unwind instruction.
llvm-svn: 140277
2011-09-21 22:14:28 +00:00
e5e189f669
X86Disassembler: if verbose logging is going to nulls(), disable logging completely.
...
Otherwise we'll spend a ridiculous amount of time pretty printing debug output and then discarding it.
llvm-svn: 140276
2011-09-21 21:47:35 +00:00
098f5a2911
Tidy up. Whitepsace.
...
llvm-svn: 140275
2011-09-21 21:36:53 +00:00
eee3afcb86
Fix some simple copy-paste errors in MBlaze ASM Parser and Makefile.
...
patch contributed by Jia Liu!
llvm-svn: 140273
2011-09-21 19:23:46 +00:00
bcc3fadad9
These do not need to be conditional on the presence of CommentStream, as they have a fallback path now.
...
llvm-svn: 140267
2011-09-21 17:58:45 +00:00
1b185f4c65
Undo a change made in r140254.
...
MipsArchVersion needs to be initialized to Mips32.
llvm-svn: 140261
2011-09-21 17:31:45 +00:00
2eeb4e5bd4
DWARF: avoid unnecessary map lookups.
...
llvm-svn: 140260
2011-09-21 17:31:42 +00:00
50f123d8e5
fix comment
...
llvm-svn: 140258
2011-09-21 17:14:40 +00:00
bcc7a92e53
MipsArchVersion does not need to be in the initialization list and MipsABI
...
should be initialized to UnknownABI.
llvm-svn: 140254
2011-09-21 16:41:43 +00:00
bc9ba30158
[VECTOR-SELECT] Address one of the bugs in pr10902.
...
Vector SetCC result types need to be type-legalized.
This code worked before because scalar result types are known to be legal.
llvm-svn: 140249
2011-09-21 14:34:38 +00:00
c1cd8506ce
Insert a sanity check on the combining of x86 truncing-store nodes. This comes to replace the problematic check that was removed in r139995.
...
llvm-svn: 140246
2011-09-21 08:45:10 +00:00
a318b8dce6
Change:
...
assert(!"error message");
To:
assert(0 && "error message");
which is more consistant across the code base.
llvm-svn: 140234
2011-09-21 03:09:09 +00:00
3d673cc323
Add a base class for Mips TargetMachines and add Mips64 TargetMachines.
...
llvm-svn: 140233
2011-09-21 03:00:58 +00:00
6de4d12120
Set ABI if it hasn't been set on the command line.
...
Check if architecture & ABI combination is valid.
llvm-svn: 140230
2011-09-21 02:45:29 +00:00
6e506eb57d
Fix typo.
...
llvm-svn: 140229
2011-09-21 02:24:25 +00:00
924123acb3
Lower ARM adds/subs to add/sub after adding optional CPSR operand.
...
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.
llvm-svn: 140228
2011-09-21 02:20:46 +00:00
3f1fdf1b31
whitespace
...
llvm-svn: 140227
2011-09-21 02:17:37 +00:00
69fa8ffeef
In the disassembler C API, be careful not to confuse the comment streamer that the disassembler outputs annotations on with the streamer that the InstPrinter will print them on.
...
llvm-svn: 140217
2011-09-21 00:25:23 +00:00
bb49e721b8
Change the names of functions isMips* to hasMips*.
...
llvm-svn: 140214
2011-09-20 23:53:09 +00:00
1815b688cc
Make sure IPSCCP never marks a tracked call as overdefined in SCCPSolver::ResolvedUndefsIn. If we do, we can end up in a situation where a function is resolved to return a constant, but the caller is marked overdefined, which confuses the code later.
...
<rdar://problem/9956541> (again).
llvm-svn: 140210
2011-09-20 23:28:51 +00:00
6cb23f6e7f
Add a DAGCombine for subvector extracts to remove useless chains of
...
subvector inserts and extracts. Initial patch by Rackover, Zvi with
some tweak done by me.
llvm-svn: 140204
2011-09-20 23:19:33 +00:00
8058234b32
Revert r140097, working on a better approach
...
llvm-svn: 140203
2011-09-20 23:19:29 +00:00
5227ea6028
lib/Linker: add support of deps which does not end with ".so".
...
It happens (for example) when you want to have a dependency on the .so
with the specific version, like liblzma.so.1.0.0 or
libcrypto.so.0.9.8.
llvm-svn: 140201
2011-09-20 22:52:35 +00:00
f7638e1e51
Simplify max/minp[s|d] dagcombine matching
...
llvm-svn: 140199
2011-09-20 22:34:45 +00:00
a6e1c51ed7
Relax this condition.
...
Some passes require breaking critical edges before they're called. Don't
segfault because of that.
llvm-svn: 140196
2011-09-20 22:28:17 +00:00
04289fcad8
Place the check for an exit landing pad where it will be run on both code paths through the if-then-else.
...
llvm-svn: 140195
2011-09-20 22:27:16 +00:00
0058520770
Omit extracting a loop if one of the exits is a landing pad.
...
The landing pad must accompany the invoke when it's extracted. However, if it
does, then the loop isn't properly extracted. I.e., the resulting extraction has
a loop in it. The extracted function is then extracted, etc. resulting in an
infinite loop.
llvm-svn: 140193
2011-09-20 22:23:09 +00:00
49621cb209
Remove the hack to check UNAME_RELEASE when identifying the Darwin version.
...
This was only needed to locate llvm-gcc's installation directory when clang
falls back to run llvm-gcc for i386 kexts. As of clang svn r140187, we're
now just searching paths with several different Darwin versions on either
side of the current version, so this is no longer needed.
llvm-svn: 140188
2011-09-20 22:05:56 +00:00
60aa85b672
Tidy up a bit more, fix tab and remove trailing whitespaces
...
llvm-svn: 140186
2011-09-20 21:45:26 +00:00
33e91a6cf7
The wrong relocation was being emitted for several SSSE3 instructions.
...
This fixes PR10963. Thanks to Benjamin for finding the wrong tablegen
declaration.
llvm-svn: 140184
2011-09-20 21:39:21 +00:00
05f3f4939a
Tidy up code!
...
llvm-svn: 140183
2011-09-20 21:39:06 +00:00
61a003315e
Fix a bug introduced during refactoring a couple of months ago. Cortex-M3 does not support Thumb2 dsp instructions. rdar://10152911.
...
llvm-svn: 140181
2011-09-20 21:38:18 +00:00
2b37261fd6
Initial Mips64 support. Patch by Liu with some modifications.
...
llvm-svn: 140178
2011-09-20 20:28:08 +00:00
3d48f59231
Check the terminator, not the basic block.
...
llvm-svn: 140176
2011-09-20 20:20:50 +00:00
c1da6ea344
When extracting a basic block that ends in an 'invoke' instruction, we need to
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extract its associated landing pad block as well. However, that landing pad
block may have more than one predecessor. So split the landing pad block so that
individual landing pads have only one predecessor.
This type of transformation may produce a false positive with bugpoint.
llvm-svn: 140173
2011-09-20 19:10:24 +00:00
fc1176e061
Use ArrayRef instead of an explicit 'const std::vector &'.
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llvm-svn: 140172
2011-09-20 19:05:04 +00:00
7d06f5cdd4
If simple ownership works then friendship is not required.
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llvm-svn: 140169
2011-09-20 18:48:56 +00:00
1bfe55a378
Use ArrayRef instead of 'const std::vector' to pass around the list of basic blocks to extract.
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llvm-svn: 140168
2011-09-20 18:42:07 +00:00
add1f17575
Update GCOVLines to provide interfaces to write line table and calculate complete length.
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llvm-svn: 140167
2011-09-20 18:35:00 +00:00
c98ac850eb
U is good enough
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llvm-svn: 140166
2011-09-20 18:33:29 +00:00
9a2ba72c49
Fix comments.
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llvm-svn: 140164
2011-09-20 18:24:46 +00:00
52363bdbeb
Restore hasPostISelHook tblgen flag.
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No functionality change. The hook makes it explicit which patterns
require "special" handling. i.e. it self-documents tblgen
deficiencies. I plan to add verification in ExpandISelPseudos and
Thumb2SizeReduce to catch any missing hasPostISelHooks. Otherwise it's
too fragile.
llvm-svn: 140160
2011-09-20 18:22:31 +00:00
e4e20f43e4
Eliminate sign-comparison warnings in APInt
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llvm-svn: 140158
2011-09-20 18:11:52 +00:00
6c3ad65288
Add mips64 & mips64el to Triple. Patch by Liu with modifications.
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llvm-svn: 140157
2011-09-20 18:09:37 +00:00
1a155a8200
Update comment.
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llvm-svn: 140156
2011-09-20 18:05:45 +00:00
9cb1fc034b
Use StringRef instead of std::string.
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llvm-svn: 140154
2011-09-20 17:55:19 +00:00
972df96ab1
Eliminate unnecessary copy of FileName from GCOVLines.
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GCOVLines is always accessed through a StringMap where the key is FileName.
llvm-svn: 140151
2011-09-20 17:43:14 +00:00
b011105d6c
There is no need to write a local utility routine to find subprogram info if the utility routine is already available in DebugInfo.
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llvm-svn: 140145
2011-09-20 15:57:19 +00:00
68c92d86da
Extend changes from r139986 to produce 256-bit AVX minps/minpd/maxps/maxpd.
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llvm-svn: 140140
2011-09-20 07:38:59 +00:00
8586e62d91
ARM isel bug fix for adds/subs operands.
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Modified ARMISelLowering::AdjustInstrPostInstrSelection to handle the
full gamut of CPSR defs/uses including instructins whose "optional"
cc_out operand is not really optional. This allowed removal of the
hasPostISelHook to simplify the .td files and make the implementation
more robust.
Fixes rdar://10137436: sqlite3 miscompile
llvm-svn: 140134
2011-09-20 03:17:40 +00:00
53df4b6dfa
whitespace
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llvm-svn: 140133
2011-09-20 03:06:13 +00:00
Akira Hatanaka