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50246 Commits

Author SHA1 Message Date
NAKAMURA Takumi f995985eba lib/DebugInfo/DWARFDebugLine.cpp: De-Unicode-ify. 
llvm-svn: 141484
 2011-10-08 11:22:47 +00:00
NAKAMURA Takumi ade616cb57 Whitespace 
llvm-svn: 141483
 2011-10-08 11:22:41 +00:00
Anton Korobeynikov e45373520d Disable ABS optimization for Thumb1 target, we don't have necessary instructions there. 
llvm-svn: 141481
 2011-10-08 08:38:45 +00:00
Akira Hatanaka 6be7d6c976 Simplify definition of FP move instructions. 
llvm-svn: 141476
 2011-10-08 03:50:18 +00:00
Akira Hatanaka 2365f90676 Define classes and multiclasses for FP binary instructions. 
llvm-svn: 141475
 2011-10-08 03:38:41 +00:00
Akira Hatanaka c7548dec7d Define multiclasses for FP-to-FP instructions. 
llvm-svn: 141474
 2011-10-08 03:29:22 +00:00
Akira Hatanaka 13ae13bdc2 Define classes for FP unary instructions and multiclasses for FP-to-fixed point 
conversion instructions. 

llvm-svn: 141473
 2011-10-08 03:19:38 +00:00
Akira Hatanaka 557c8e3443 Add patterns for unaligned load and store instructions and enable the 
instruction selector to generate them.

llvm-svn: 141471
 2011-10-08 02:24:10 +00:00
Andrew Trick eef7308df6 Add an extra safety check in front of the optimization in r141442. 
llvm-svn: 141470
 2011-10-08 02:16:39 +00:00
Bill Wendling e9574be6a3 Use the code that lowers the arguments and spills any values which are alive 
across unwind edges. This is for the back-end which expects such things.

The code is from the original SjLj EH pass.

llvm-svn: 141463
 2011-10-08 00:56:47 +00:00
Michael J. Spencer 159970f733 Object: Add support for opening stdin. 
llvm-svn: 141449
 2011-10-08 00:17:58 +00:00
Michael J. Spencer 7eb8159927 Object: constize Archive. 
llvm-svn: 141448
 2011-10-08 00:17:45 +00:00
Jim Grosbach d0637bfc68 ARM NEON assembly parsing and encoding for VDUP(scalar). 
llvm-svn: 141446
 2011-10-07 23:56:00 +00:00
Andrew Trick 7fb669ab48 LSR should only reuse phis that match its formula. 
Fixes rdar://problem/5064068

llvm-svn: 141442
 2011-10-07 23:46:21 +00:00
Eli Friedman 195464184e Fix APInt::operator*= so that it computes the correct result for large integers where there is unsigned overflow. Fix APFloat::toString so that it doesn't depend on the incorrect behavior in common cases (and computes the correct result in some rare cases). Fixes PR11086. 
llvm-svn: 141441
 2011-10-07 23:40:49 +00:00
Nick Lewycky 133a16871f Don't emit the symbol table entry for the .symtab_shndx section either. 
llvm-svn: 141440
 2011-10-07 23:29:53 +00:00
Nick Lewycky c6ac5f7388 Remove extraneous curlies. No functionality change. 
llvm-svn: 141439
 2011-10-07 23:28:32 +00:00
Jim Grosbach 6e5778f7b1 ARM prefix asmparser operand kind enums for readability. 
llvm-svn: 141438
 2011-10-07 23:24:09 +00:00
Bill Wendling 883ec97115 Take all of the invoke basic blocks and make the dispatch basic block their new 
successor. Remove the old landing pad from their successor list, because it's
now the successor of the dispatch block. Now that the landing pad blocks are no
longer the destination of invokes, we can mark them as normal basic blocks
instead of landing pads.

This more closely resembles what the CFG is actually doing.

llvm-svn: 141436
 2011-10-07 23:18:02 +00:00
Bill Wendling f9f5e455d4 Take the code that was emitted for the llvm.eh.dispatch.setup intrinsic and emit 
it with the new SjLj emitter stuff. This way there's no need to emit that
kind-of-hacky intrinsic.

llvm-svn: 141419
 2011-10-07 22:08:37 +00:00
Bill Wendling 7ecfbd90ef Thread the chain through the eh.sjlj.setjmp intrinsic, like it's documented to 
do. This will be useful later on with the new SJLJ stuff.

llvm-svn: 141416
 2011-10-07 21:25:38 +00:00
Nick Lewycky 8b02d36a23 Don't emit a shstrtabindex in the reserved range. Spotted by inspection and 
patch by Cary Coutant!

llvm-svn: 141413
 2011-10-07 20:58:24 +00:00
Nick Lewycky 4eb1143038 Clarify/fix typo. No functionality change. 
llvm-svn: 141412
 2011-10-07 20:56:23 +00:00
Jakob Stoklund Olesen 464fcc0035 Constrain both operands on MOVZX32_NOREXrr8. 
This instruction is explicitly encoded without an REX prefix, so both
operands but be *_NOREX.

Also add an assertion to copyPhysReg() that fires when the MOV8rr_NOREX
constraints are not satisfied.

This fixes a miscompilation in 20040709-2 in the gcc test suite.

llvm-svn: 141410
 2011-10-07 20:15:54 +00:00
Michael J. Spencer cfb6cc7b14 Fix GCC again. 
llvm-svn: 141389
 2011-10-07 19:46:12 +00:00
Michael J. Spencer e5fd004719 Change relocation API to be per section. This time without breaking GCC. 
llvm-svn: 141385
 2011-10-07 19:25:32 +00:00
Jim Grosbach b8d9f51e4c Improve ARM assembly parser diagnostic for unexpected tokens. 
Consider:
  mov r8, r11 fred

Previously, we issued the not very informative:
x.s:6:1: error: unexpected token in argument list

^

Now we generate:
x.s:5:14: error: unexpected token in argument list
  mov r8, r11 fred
              ^

llvm-svn: 141380
 2011-10-07 18:27:04 +00:00
Bill Wendling 206d8a7f48 Revert 141376 and 141377 due to breaking the build. 
--- Reverse-merging r141377 into '.':
U    tools/llvm-objdump/MachODump.cpp
--- Reverse-merging r141376 into '.':
U    include/llvm/Object/COFF.h
U    include/llvm/Object/ObjectFile.h
U    include/llvm-c/Object.h
U    tools/llvm-objdump/llvm-objdump.cpp
U    lib/Object/MachOObjectFile.cpp
U    lib/Object/COFFObjectFile.cpp
U    lib/Object/Object.cpp
U    lib/Object/ELFObjectFile.cpp

llvm-svn: 141379
 2011-10-07 18:25:37 +00:00
David Greene 33f619971f Remove Multidefs 
Multidefs are a bit unwieldy and incomplete.  Remove them in favor of
another mechanism, probably for loops.

Revert "Make Test More Thorough"
Revert "Fix a typo."
Revert "Vim Support for Multidefs"
Revert "Emacs Support for Multidefs"
Revert "Document Multidefs"
Revert "Add a Multidef Test"
Revert "Update Test for Multidefs"
Revert "Process Multidefs"
Revert "Parser Multidef Support"
Revert "Lexer Support for Multidefs"
Revert "Add Multidef Data Structures"

llvm-svn: 141378
 2011-10-07 18:25:05 +00:00
Michael J. Spencer b0d61540cb Change relocation API to be per section. 
llvm-svn: 141376
 2011-10-07 18:15:25 +00:00
Evan Cheng 74db300f37 High bits of movmskp{s|d} and pmovmskb are known zero. rdar://10247336 
llvm-svn: 141371
 2011-10-07 17:21:44 +00:00
Bob Wilson 8decdc472f Reenable tail calls for iOS 5.0 and later. 
llvm-svn: 141370
 2011-10-07 17:17:49 +00:00
Bob Wilson bc1589945d Reenable use of divmod compiler_rt functions for iOS 5.0 and later. 
llvm-svn: 141368
 2011-10-07 16:59:21 +00:00
Matt Beaumont-Gay b7609cd35f Move default to top of switch 
llvm-svn: 141366
 2011-10-07 16:27:01 +00:00
Anton Korobeynikov 318d6bae80 Peephole optimization for ABS on ARM. 
Patch by Ana Pazos!

llvm-svn: 141365
 2011-10-07 16:15:08 +00:00
Duncan Sands c52af46484 Teach GVN to also propagate switch cases. For example, in this code 
switch (n) {
    case 27:
      do_something(x);
    ...
  }
the call do_something(x) will be replaced with do_something(27).  In
gcc-as-one-big-file this results in the removal of about 500 lines of
bitcode (about 0.02%), so has about 1/10 of the effect of propagating
branch conditions.

llvm-svn: 141360
 2011-10-07 08:29:06 +00:00
Craig Topper d9cfddc5cd Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE. 
llvm-svn: 141358
 2011-10-07 07:02:24 +00:00
Andrew Trick 35c9e51219 PostRA scheduler fix. Clear stale loop dependencies. 
Fixes <rdar://problem/10235725>

llvm-svn: 141357
 2011-10-07 06:33:09 +00:00
Andrew Trick 4ef158335b whitespace 
llvm-svn: 141356
 2011-10-07 06:27:02 +00:00
Craig Topper bf136764ae Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT. 
llvm-svn: 141354
 2011-10-07 05:53:50 +00:00
Craig Topper 5aebebe18d Revert part of r141274. Only need to change encoding for xchg %eax, %eax in 64-bit mode. This is because in 64-bit mode xchg %eax, %eax implies zeroing the upper 32-bits of RAX which makes it not a NOP. In 32-bit mode using NOP encoding is fine. 
llvm-svn: 141353
 2011-10-07 05:35:38 +00:00
Bill Wendling 8d50ea0f82 Use the correct vreg here. 
llvm-svn: 141342
 2011-10-06 23:41:14 +00:00
Bill Wendling b3d4678877 Generate the dispatch code for a 'thumb' function. This is very similar to the 
others. They take the call site value. Determine if it's a proper value. And
then jumps to the correct call site via a jump table.

llvm-svn: 141341
 2011-10-06 23:37:36 +00:00
Owen Anderson 6a5c150e9c Fix the check for nested IT instructions in the disassembler. We need to perform the check before adding the Thumb predicate, which pops on entry off the ITBlock queue. 
llvm-svn: 141339
 2011-10-06 23:33:11 +00:00
Eli Friedman 1456cd20b4 Remove the old atomic instrinsics. autoupgrade functionality is included with this patch. 
llvm-svn: 141333
 2011-10-06 23:20:49 +00:00
Bill Wendling 5626c66a89 Generate the dispatch table for ARM mode. 
llvm-svn: 141327
 2011-10-06 22:53:00 +00:00
Bill Wendling 030b58e5c9 Refactor some of the code that sets up the entry block for SjLj EH. No functionality change. 
llvm-svn: 141323
 2011-10-06 22:18:16 +00:00
Bill Wendling 31d973cde6 Use a thumb ORR instead of thumb2 ORR when in thumb-only mode. (Picky! Picky!) 
Place the immediate to OR into a register so that it works.

llvm-svn: 141319
 2011-10-06 21:51:21 +00:00
Bill Wendling 362c1b01cc * Set the low bit of the return address when we are in thumb mode. 
* Some code cleanup.

llvm-svn: 141317
 2011-10-06 21:29:56 +00:00
David Greene 7475ad05fa Fix List-of-List Processing 
Fix VarListElementInit::resolveListElementReference to return a
partially resolved VarListElementInint in the case where full
resolution is not possible.  This allows TableGen to make forward
progress resolving certain complex list expressions.

llvm-svn: 141315
 2011-10-06 21:20:46 +00:00