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11 Commits

Author SHA1 Message Date
Chad Rosier e0e38f61a5 When performing a truncating store, it's possible to rearrange the data 
in-register, such that we can use a single vector store rather then a 
series of scalar stores.

For func_4_8 the generated code

	vldr	d16, LCPI0_0
	vmov	d17, r0, r1
	vadd.i16	d16, d17, d16
	vmov.u16	r0, d16[3]
	strb	r0, [r2, #3]
	vmov.u16	r0, d16[2]
	strb	r0, [r2, #2]
	vmov.u16	r0, d16[1]
	strb	r0, [r2, #1]
	vmov.u16	r0, d16[0]
	strb	r0, [r2]
	bx	lr

becomes

	vldr	d16, LCPI0_0
	vmov	d17, r0, r1
	vadd.i16	d16, d17, d16
	vuzp.8	d16, d17
	vst1.32	{d16[0]}, [r2, :32]
	bx	lr

I'm not fond of how this combine pessimizes 2012-03-13-DAGCombineBug.ll,
but I couldn't think of a way to judiciously apply this combine.

This

	ldrh	r0, [r0, #4]
	strh	r0, [r1]

becomes

	vldr	d16, [r0]
	vmov.u16	r0, d16[2]
	vmov.32	d16[0], r0
	vuzp.16	d16, d17
	vst1.32	{d16[0]}, [r1, :32]

PR11158
rdar://10703339

llvm-svn: 154340
 2012-04-09 20:32:02 +00:00
Nadav Rotem d2c72d6d03 Add CHECKs and document PR11158. 
llvm-svn: 142240
 2011-10-17 20:23:23 +00:00
Nadav Rotem 486ff59a9f Enable element promotion type legalization by deafault. 
Changed tests which assumed that vectors are legalized by widening them.

llvm-svn: 142152
 2011-10-16 20:31:33 +00:00
Tanya Lattner 1d11720ae4 Handle perfect shuffle case that generates a vrev for vectors of floats. 
Add test case.

llvm-svn: 131582
 2011-05-18 21:44:54 +00:00
Tanya Lattner 48b182c3a4 In r131488 I misunderstood how VREV works. It splits the vector in half and splits each half. Therefore, the real problem was that we were using a VREV64 for a 4xi16, when we should have been using a VREV32. 
Updated test case and reverted change to the PerfectShuffle Table.

llvm-svn: 131529
 2011-05-18 06:42:21 +00:00
Tanya Lattner c7e291b354 vrev is incorrectly defined in the perfect shuffle table. The ordering is backwards (should be 0x3210 versus 0x1032) which exposed a bug when doing a shuffle on a 4xi16. I've attached a test case. 
llvm-svn: 131488
 2011-05-17 20:48:40 +00:00
Bob Wilson c7334a146e SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482
 2010-10-27 20:38:28 +00:00
Bob Wilson 411dfad981 Allow more cases of undef shuffle indices and add tests for them. 
llvm-svn: 111226
 2010-08-17 05:54:34 +00:00
Rafael Espindola 29dda21e96 Remove arm_apcscc from the test files. It is the default and doing this 
matches what llvm-gcc and clang now produce.

llvm-svn: 106221
 2010-06-17 15:18:27 +00:00
Dan Gohman c8054d90fb Eliminate more uses of llvm-as and llvm-dis. 
llvm-svn: 81293
 2009-09-09 00:09:15 +00:00
Bob Wilson 8a37bbebfd Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.

llvm-svn: 77101
 2009-07-26 00:39:34 +00:00