cc7763ba92
Hexagon: Fold a single-use textual header into its use
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llvm-svn: 316604
2017-10-25 19:52:21 +00:00
557729761c
[Hexagon] Switch to parameterized register classes for HVX
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This removes the duplicate HVX instruction set for the 128-byte mode.
Single instruction set now works for both modes (64- and 128-byte).
llvm-svn: 313362
2017-09-15 15:46:05 +00:00
e4fc6ee790
[Hexagon] Fix some Clang-tidy modernize-use-using and Include What You Use warnings; other minor fixes (NFC).
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llvm-svn: 309230
2017-07-26 23:20:35 +00:00
6bda14b313
Sort the remaining #include lines in include/... and lib/....
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I did this a long time ago with a janky python script, but now
clang-format has built-in support for this. I fed clang-format every
line with a #include and let it re-sort things according to the precise
LLVM rules for include ordering baked into clang-format these days.
I've reverted a number of files where the results of sorting includes
isn't healthy. Either places where we have legacy code relying on
particular include ordering (where possible, I'll fix these separately)
or where we have particular formatting around #include lines that
I didn't want to disturb in this patch.
This patch is *entirely* mechanical. If you get merge conflicts or
anything, just ignore the changes in this patch and run clang-format
over your #include lines in the files.
Sorry for any noise here, but it is important to keep these things
stable. I was seeing an increasing number of patches with irrelevant
re-ordering of #include lines because clang-format was used. This patch
at least isolates that churn, makes it easy to skip when resolving
conflicts, and gets us to a clean baseline (again).
llvm-svn: 304787
2017-06-06 11:49:48 +00:00
e260332838
[Hexagon] Remove C6 and C7 as separate registers
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These are M0 and M1. Removing duplicated registers reduces the number
of explicit register aliasing.
llvm-svn: 302306
2017-05-05 22:12:12 +00:00
e12d1e70cb
[Hexagon] Improve shuffle error reporting
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Patch by Colin LeMahieu.
llvm-svn: 301823
2017-05-01 19:41:43 +00:00
058abf1a4a
[Hexagon] Change the vector scaling for vector offsets
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Keep full offset value on MI-level instructions, but have it scaled down
in the MC-level instructions.
llvm-svn: 299664
2017-04-06 17:28:21 +00:00
ab57c2bad3
[Hexagon] Implement @llvm.readcyclecounter()
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llvm-svn: 295892
2017-02-22 22:28:47 +00:00
f9015e62fd
[Hexagon] Introduce Hexagon V62
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llvm-svn: 294805
2017-02-10 23:46:45 +00:00
a72fad980c
[Hexagon] Replace instruction definitions with auto-generated ones
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llvm-svn: 294753
2017-02-10 15:33:13 +00:00
f65b8f14f4
[Hexagon] Rename TypeCOMPOUND to TypeCJ
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llvm-svn: 293894
2017-02-02 15:03:30 +00:00
8208592707
[Hexagon] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
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llvm-svn: 289604
2016-12-13 22:13:50 +00:00
8170754919
[Hexagon] Changing from literal numeric value to argument since #-1 will not parse when '-' is converted to a token.
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llvm-svn: 288634
2016-12-05 04:29:00 +00:00
4e76019e34
Support: Remove MemoryObject and DataStreamer interfaces.
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These interfaces are no longer used.
Differential Revision: https://reviews.llvm.org/D26222
llvm-svn: 285774
2016-11-02 00:08:37 +00:00
654dc11b79
[Hexagon] Rename operand/predicate names for unshifted integers
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For example, rename s6Ext to s6_0Ext. The names for shifted integers
include the underscore and this will make the naming consistent. It
also exposed a few duplicates that were removed.
llvm-svn: 285728
2016-11-01 19:02:10 +00:00
f42454b94b
Move the global variables representing each Target behind accessor function
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This avoids "static initialization order fiasco"
Differential Revision: https://reviews.llvm.org/D25412
llvm-svn: 283702
2016-10-09 23:00:34 +00:00
8ed1aee9dd
[Hexagon] NFC Removing 'V4_' prefix from duplex instruction names.
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llvm-svn: 283514
2016-10-07 00:15:07 +00:00
9675de5ba8
[Hexagon] NFC. Canonicalizing absolute address instruction names.
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llvm-svn: 283507
2016-10-06 23:02:11 +00:00
73e0ad8220
[Hexagon] Fix disassembler crash after r279255
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When p0 was added as an explicit operand to the duplex subinstructions,
the disassembler was not updated to reflect this.
llvm-svn: 281104
2016-09-09 21:45:00 +00:00
b550cb1750
[NFC] Header cleanup
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Removed some unused headers, replaced some headers with forward class declarations.
Found using simple scripts like this one:
clear && ack --cpp -l '#include "llvm/ADT/IndexedMap.h"' | xargs grep -L 'IndexedMap[<]' | xargs grep -n --color=auto 'IndexedMap'
Patch by Eugene Kosov <claprix@yandex.ru>
Differential Revision: http://reviews.llvm.org/D19219
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 266595
2016-04-18 09:17:29 +00:00
bb0cdfb9f7
[Hexagon] Adding missing break in switch statement. Extra operands would have been appended to the end.
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llvm-svn: 263657
2016-03-16 20:00:38 +00:00
2d497a0078
[NFC] Convert tabs to spaces.
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llvm-svn: 262411
2016-03-01 22:05:03 +00:00
6fdfa3dc32
[NFC] Referencing manual for reason why subregbit is checked
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llvm-svn: 259380
2016-02-01 18:15:39 +00:00
f57c1977c1
Reflect the MC/MCDisassembler split on the include/ level.
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No functional change, just moving code around.
llvm-svn: 258818
2016-01-26 16:44:37 +00:00
e5e035a3a8
Replace uint16_t with the MCPhysReg typedef in many places. A lot of physical register arrays already use this typedef.
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llvm-svn: 254843
2015-12-05 07:13:35 +00:00
d824f5f0d9
[Hexagon] Use array_lengthof and const correct and type correct the array and array size. NFC
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llvm-svn: 254384
2015-12-01 06:13:08 +00:00
6261e1b94d
Use array_lengthof instead of manually calculating it. NFC
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llvm-svn: 254383
2015-12-01 06:13:06 +00:00
3da000c07f
[Hexagon] Use ArrayRef to avoid needing to calculate an array size. Interestingly the original code may have had a bug because it was passing the byte size of a uint16_t array instead of the number of entries.
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llvm-svn: 254382
2015-12-01 06:13:04 +00:00
f0af6e5243
[Hexagon] Factoring bundle creation in to a utility function.
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llvm-svn: 253056
2015-11-13 17:42:46 +00:00
7cd0892729
[Hexagon] Enabling ASM parsing on Hexagon backend and adding instruction parsing tests. General updating of the code emission.
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llvm-svn: 252443
2015-11-09 04:07:48 +00:00
160f73e36f
[Hexagon] Fixing mistaken case fallthrough.
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llvm-svn: 251867
2015-11-03 00:21:19 +00:00
7c9587136d
[Hexagon] Adding skeleton of HVX extension instructions.
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llvm-svn: 250600
2015-10-17 01:33:04 +00:00
f97999dc46
Explicitly clear the MI operand list when getInstruction() is called. Call MI.clear() within MCD::OPC_Decode case and inside of translateInstruction() for the X86 target. Remove now unnecessary MI.clear() from ARMDisassembler.
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Summary: Explicitly clear the MI operand list when getInstruction() is called.
Reviewers: hfinkel, t.p.northover, hvarga, kparzysz, jyknight, qcolombet, uweigand
Subscribers: llvm-commits
Differential Revision: http://reviews.llvm.org/D11665
llvm-svn: 244557
2015-08-11 01:15:07 +00:00
f00654e31b
Revert r240137 (Fixed/added namespace ending comments using clang-tidy. NFC)
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Apparently, the style needs to be agreed upon first.
llvm-svn: 240390
2015-06-23 09:49:53 +00:00
70bc5f1398
Fixed/added namespace ending comments using clang-tidy. NFC
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The patch is generated using this command:
tools/clang/tools/extra/clang-tidy/tool/run-clang-tidy.py -fix \
-checks=-*,llvm-namespace-comment -header-filter='llvm/.*|clang/.*' \
llvm/lib/
Thanks to Eugene Kosov for the original patch!
llvm-svn: 240137
2015-06-19 15:57:42 +00:00
1e9d1d768c
[Hexagon] Adding decoders for signed operands and ensuring all signed operand types disassemble correctly.
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llvm-svn: 239477
2015-06-10 16:52:32 +00:00
be8c453d58
[Hexagon] Reapply r239097 with tests corrected for shuffling and duplexing.
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llvm-svn: 239161
2015-06-05 16:00:11 +00:00
c40be85adc
Revert r239095 incorrect test tree.
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llvm-svn: 239102
2015-06-04 21:32:42 +00:00
fc52c11d80
[Hexagon] Adding functionality for duplexing. Duplexing is a way to compress commonly used pairs of instructions in order to reduce code size. The test case duplex.ll normally would be 8 bytes, assign register to 0 and jump to link register. After duplexing this is only 4 bytes. This also tests the HexagonMCShuffler code path which is used to make sure duplexed instructions still follow slot requirements.
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llvm-svn: 239095
2015-06-04 21:16:16 +00:00
68d967d92e
[Hexagon] Disassembling, printing, and emitting instructions a whole-bundle at a time which is the semantic unit for Hexagon. Fixing tests to use the new format. Disabling tests in the direct object emission path for a followup patch.
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llvm-svn: 238556
2015-05-29 14:44:13 +00:00
e9119e41ef
MC: Modernize MCOperand API naming. NFC.
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MCOperand::Create*() methods renamed to MCOperand::create*().
llvm-svn: 237275
2015-05-13 18:37:00 +00:00
1174fea31c
[Hexagon] Moving remaining methods off of HexagonMCInst in to HexagonMCInstrInfo and eliminating HexagonMCInst class.
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llvm-svn: 229914
2015-02-19 21:10:50 +00:00
404d5b242d
[Hexagon] Adding vector load with post-increment instructions. Adding decoder function for 64bit control register class.
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llvm-svn: 228708
2015-02-10 16:59:36 +00:00
d9903888d9
[cleanup] Re-sort all the #include lines in LLVM using
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utils/sort_includes.py.
I clearly haven't done this in a while, so more changed than usual. This
even uncovered a missing include from the InstrProf library that I've
added. No functionality changed here, just mechanical cleanup of the
include order.
llvm-svn: 225974
2015-01-14 11:23:27 +00:00
ff370ed90e
[Hexagon] Adding deallocframe and circular addressing loads.
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llvm-svn: 224869
2014-12-26 20:30:58 +00:00
f3db884efb
[Hexagon] Adding transfers to and from control registers.
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llvm-svn: 224599
2014-12-19 19:06:32 +00:00
383c36e3a8
[Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding combine imm-imm form.
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llvm-svn: 223494
2014-12-05 18:24:06 +00:00
5d6f03bd5a
[Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests.
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llvm-svn: 223334
2014-12-04 03:41:21 +00:00
efa74e0280
[Hexagon] Converting from ADD_rr to A2_add which has encoding bits.
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Adding test to show correct instruction selection and encoding.
llvm-svn: 222249
2014-11-18 20:28:11 +00:00
7fc5b87480
Pass an ArrayRef to MCDisassembler::getInstruction.
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With this patch MCDisassembler::getInstruction takes an ArrayRef<uint8_t>
instead of a MemoryObject.
Even on X86 there is a maximum size an instruction can have. Given
that, it seems way simpler and more efficient to just pass an ArrayRef
to the disassembler instead of a MemoryObject and have it do a virtual
call every time it wants some extra bytes.
llvm-svn: 221751
2014-11-12 02:04:27 +00:00
David Blaikie