WriteFlags() and renamed WriteCoreRegisterWithFlags() to WriteCoreRegOptionalFlags().
Modified the call sites to use the helper methods.
llvm-svn: 125788
Renamed EmulateAddRdnRm() to EmulateAddReg(), and added Encoding T1 to it.
Where Encoding T2 can potentially modify the PC, causing a brnach.
llvm-svn: 125782
and unaligned memory accesses. The new stub functions are MemARead, MemAWrite,
MemURead, and MemUWrite. At the moment these stubs just call ReadMemoryUnsigned or
WriteMemoryUnsigned, but we can fill them out further later if we decide we need
more accurate emulation of the memory system.
Replaced all the direct calls to ReadMemoryUnsigned and WriteMemoryUnsigned in
EmulateInstructionARM.cpp with calls to the appropriate new stub function.
llvm-svn: 125766
// if d == 15 then // Can only occur for encoding A1
// ALUWritePC(result); // setflags is always FALSE here
// else
// R[d] = result;
// if setflags then
// APSR.N = result<31>;
// APSR.Z = IsZeroBit(result);
// APSR.C = carry;
// // APSR.V unchanged
into a helper method WriteCoreRegisterWithFlags, and modified the existing methods
to take advantage of it.
Plus add two emulation methods (declaration only for now) for ORR (immediate) and ORR (register).
llvm-svn: 125701
clang_type_t
GetClangFullType(); // Get a completely defined clang type
clang_type_t
GetClangLayoutType(); // Get a clang type that can be used for type layout
clang_type_t
GetClangForwardType(); // A type that can be completed if needed, but is more efficient.
llvm-svn: 125691
Turns out that they can be funneled through the helper methods
EmulateShiftImm()/ EmulateShiftReg() as well.
Modify EmulateShiftImm() to handle SRType_ROR and SRType_RRX.
And fix a typo in the impl of utility Shift_C() in ARMUtils.h.
llvm-svn: 125689
This patch reverts a portion of r125199 to allow the tree to build again on
linux. The specific mingw issues that revision intended to address can be
sorted out at a later time.
llvm-svn: 125655
it should live and the lldb_private::Process takes care of managing the
auto pointer to the dynamic loader instance.
Also, now that the ArchSpec contains the target triple, we are able to
correctly set the Target architecture in DidLaunch/DidAttach in the subclasses,
and then the lldb_private::Process will find the dynamic loader plug-in
by letting the dynamic loader plug-ins inspect the arch/triple in the target.
So now the ProcessGDBRemote plug-in is another step closer to be purely
process/platform agnostic.
I updated the ProcessMacOSX and the ProcessLinux plug-ins accordingly.
llvm-svn: 125650
Create two helper methods EmulateShiftImm() and EmulateShiftReg() and have ASR, LSL, and LSR
delegate to the helper methods which take an extra ARM_ShifterType parameter.
The opcodes tables have not been updated yet to reflect these new entries.
llvm-svn: 125633
now, in addition to cpu type/subtype and architecture flavor, contains:
- byte order (big endian, little endian)
- address size in bytes
- llvm::Triple for true target triple support and for more powerful plug-in
selection.
llvm-svn: 125602
ArchDefaultUnwindPlan plug-in interfaces are now cached per architecture
instead of being leaked for every frame.
Split the ArchDefaultUnwindPlan_x86 into ArchDefaultUnwindPlan_x86_64 and
ArchDefaultUnwindPlan_i386 interfaces.
There were sporadic crashes that were due to something leaking or being
destroyed when doing stack crawls. This patch should clear up these issues.
llvm-svn: 125541
various types and numbers of arguments rather than trying to keep a
constant number of arguments for all the types.
- Also create a Register type within the instructions, to hold
register type and number.
- Modify EmulateInstructionArm.cpp to use the new register and context
types in all the instruction emulation functions.
- Add code to emulate the STM Arm instruction.
llvm-svn: 125528
table. Modify EmulateInstructionARM::EvaluateInstruction() so that if the cpsr has changed
during evaluate instruction, we flush out the change into m_inst_cpsr in preparation for the next
instruction.
llvm-svn: 125524
Johnny Chen