maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
195,564 Commits 23 Branches 0 Tags 2.2 GiB
Commit Graph

710 Commits

Author SHA1 Message Date
Colin LeMahieu 988c68f2a7 [Hexagon] Adding intrinsics for doubleword ALU operations. 
llvm-svn: 226606
 2015-01-20 20:45:05 +00:00
Colin LeMahieu 0ee02fc9fe [Hexagon] Updating muxir/ri/ii intrinsics. Setting predicate registers as compatible with i32 rather than doing custom type conversion. 
llvm-svn: 226500
 2015-01-19 20:31:18 +00:00
Colin LeMahieu fcd4569af6 [Hexagon] Converting intrinsics combine imm/imm, simple shifts and extends. 
llvm-svn: 226483
 2015-01-19 18:56:19 +00:00
Colin LeMahieu 9327bdad2f [Hexagon] Converting remaining ALU32/ALU intrinsics. 
llvm-svn: 226480
 2015-01-19 18:33:58 +00:00
Colin LeMahieu 663419b008 [Hexagon] Converting ALU32/ALU intrinsics to new patterns. 
llvm-svn: 226478
 2015-01-19 18:22:19 +00:00
Colin LeMahieu 310bad8b7e [Hexagon] Converting halfword to double accumulating multiply intrinsics. 
llvm-svn: 226472
 2015-01-19 17:36:32 +00:00
David Blaikie 9459832ebd std::unique_ptrify the MCStreamer argument to createAsmPrinter 
llvm-svn: 226414
 2015-01-18 20:29:04 +00:00
Colin LeMahieu 823415b881 [Hexagon] Converting halfword to doubleword multiply intrinsics. 
llvm-svn: 226326
 2015-01-16 21:41:57 +00:00
Colin LeMahieu cd9b276966 [Hexagon] Converting accumulating halfword multiply intrinsics to patterns. 
llvm-svn: 226324
 2015-01-16 21:36:34 +00:00
Colin LeMahieu 3b047e0ee5 [Hexagon] Beginning converting intrinsics to patterns instead of duplicated definitions. Converting halfword multiply intrinsics. 
llvm-svn: 226318
 2015-01-16 20:38:54 +00:00
Colin LeMahieu 54adb6a5d5 [Hexagon] Fix 226309, replacement atomic store patterns didn't actually exist, added new versions. 
llvm-svn: 226315
 2015-01-16 20:16:14 +00:00
Colin LeMahieu bb6718b30e [Hexagon] Removing old duplicate atomic load/store patterns. 
llvm-svn: 226309
 2015-01-16 19:53:35 +00:00
Colin LeMahieu 7d1f632380 [Hexagon] Converting old patterns to new versions using classes. 
llvm-svn: 226304
 2015-01-16 19:29:59 +00:00
Colin LeMahieu 2e3a26de0c [Hexagon] Updating call/jump instruction patterns. 
llvm-svn: 226288
 2015-01-16 17:05:27 +00:00
Colin LeMahieu cd9c4e3e07 [Hexagon] Adding new-value store and bit reverse instructions. 
llvm-svn: 226224
 2015-01-15 23:10:29 +00:00
Colin LeMahieu c59328e627 [Hexagon] Fix 226206 by uncommenting required pattern and changing patterns for simple load-extends. 
llvm-svn: 226210
 2015-01-15 21:35:49 +00:00
Colin LeMahieu f87697f05e [Hexagon] Updating indexed load-extend patterns and changing test to new expected output. 
llvm-svn: 226206
 2015-01-15 21:07:52 +00:00
Colin LeMahieu 538b85810c [Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions. 
llvm-svn: 226194
 2015-01-15 19:28:32 +00:00
Colin LeMahieu 504157f1ae [Hexagon] Adding vmux instruction. Removing old transfer instructions and updating references. 
llvm-svn: 226184
 2015-01-15 18:16:00 +00:00
Colin LeMahieu 2d1c14563e [Hexagon] Deleting old float comparison instruction and updating references to new ones. 
llvm-svn: 226179
 2015-01-15 17:28:14 +00:00
Colin LeMahieu 7959cac725 [Hexagon] Replacing old fadd/fsub instructions and updating references. 
llvm-svn: 226176
 2015-01-15 16:30:07 +00:00
Colin LeMahieu 8ffce23cda [Hexagon] Replacing old versions of stores and loads. 
llvm-svn: 226065
 2015-01-15 00:15:30 +00:00
Colin LeMahieu c7522f31f1 [Hexagon] Replacing old version of convert and load f64. 
llvm-svn: 226057
 2015-01-14 23:07:36 +00:00
Colin LeMahieu 11a34b385d [Hexagon] Removing old, unused !tstbit instructions. 
llvm-svn: 226036
 2015-01-14 20:26:15 +00:00
Colin LeMahieu c91fabc233 [Hexagon] Removing old versions of cmph and updating references. 
llvm-svn: 226013
 2015-01-14 18:26:14 +00:00
Colin LeMahieu ffacc6eac6 [Hexagon] Removing old versions of cmpb and updating references. 
llvm-svn: 226006
 2015-01-14 18:05:44 +00:00
Colin LeMahieu fa947906bf [Hexagon] Deleting versions of compare-not that don't have encoding information. Updating references. 
llvm-svn: 226003
 2015-01-14 16:49:12 +00:00
Chandler Carruth d9903888d9 [cleanup] Re-sort all the #include lines in LLVM using 
utils/sort_includes.py.

I clearly haven't done this in a while, so more changed than usual. This
even uncovered a missing include from the InstrProf library that I've
added. No functionality changed here, just mechanical cleanup of the
include order.

llvm-svn: 225974
 2015-01-14 11:23:27 +00:00
Ahmed Bougacha 2b6917b020 [SelectionDAG] Allow targets to specify legality of extloads' result 
type (in addition to the memory type).

The *LoadExt* legalization handling used to only have one type, the
memory type.  This forced users to assume that as long as the extload
for the memory type was declared legal, and the result type was legal,
the whole extload was legal.

However, this isn't always the case.  For instance, on X86, with AVX,
this is legal:
    v4i32 load, zext from v4i8
but this isn't:
    v4i64 load, zext from v4i8
Whereas v4i64 is (arguably) legal, even without AVX2.

Note that the same thing was done a while ago for truncstores (r46140),
but I assume no one needed it yet for extloads, so here we go.

Calls to getLoadExtAction were changed to add the value type, found
manually in the surrounding code.

Calls to setLoadExtAction were mechanically changed, by wrapping the
call in a loop, to match previous behavior.  The loop iterates over
the MVT subrange corresponding to the memory type (FP vectors, etc...).
I also pulled neighboring setTruncStoreActions into some of the loops;
those shouldn't make a difference, as the additional types are illegal.
(e.g., i128->i1 truncstores on PPC.)

No functional change intended.

Differential Revision: http://reviews.llvm.org/D6532

llvm-svn: 225421
 2015-01-08 00:51:32 +00:00
Colin LeMahieu 92b49c3e39 [Hexagon] Fix 225372 USR register is not fully complete. Removing Uses = [USR] maintains existing functionality to old instructions without encodings. 
llvm-svn: 225377
 2015-01-07 20:43:38 +00:00
Colin LeMahieu 627df427eb [Hexagon] Adding floating point classification and creation. 
llvm-svn: 225374
 2015-01-07 20:28:57 +00:00
Colin LeMahieu 290ece7d4c [Hexagon] Adding encodings for v5 floating point instructions. 
llvm-svn: 225372
 2015-01-07 20:24:09 +00:00
Colin LeMahieu 777abcb1d7 [Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding. 
llvm-svn: 225371
 2015-01-07 20:07:28 +00:00
Colin LeMahieu 507dd32703 [Hexagon] Adding compound jump encodings. 
llvm-svn: 225291
 2015-01-06 20:03:31 +00:00
Colin LeMahieu 68b2e050f0 [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch. 
llvm-svn: 225283
 2015-01-06 19:03:20 +00:00
Colin LeMahieu d9c605ddae [Hexagon] Adding encoding information for absolute address loads. 
llvm-svn: 225279
 2015-01-06 18:38:26 +00:00
Colin LeMahieu 243a5481d9 [Hexagon] Fix 225267. GP register is not yet fully implemented. Removing Uses [GP] maintains existing behavior. 
llvm-svn: 225270
 2015-01-06 16:52:38 +00:00
Colin LeMahieu 1445553474 [Hexagon] Adding dealloc_return encoding and absolute address stores. 
llvm-svn: 225267
 2015-01-06 16:15:15 +00:00
Colin LeMahieu dacf057bdc [Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references. 
llvm-svn: 225210
 2015-01-05 21:36:38 +00:00
Colin LeMahieu 28bb02a8c7 [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts. 
llvm-svn: 225201
 2015-01-05 20:56:41 +00:00
Colin LeMahieu abdf2b37d8 [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits. 
llvm-svn: 225199
 2015-01-05 20:35:54 +00:00
Colin LeMahieu 3acfddd6b5 [Hexagon] Adding V4 logic-logic instructions and tests. 
llvm-svn: 225198
 2015-01-05 20:14:58 +00:00
Colin LeMahieu ff10c8c95c [Hexagon] Adding orand, bitsplit reg/reg, and modwrap instructions. 
llvm-svn: 225197
 2015-01-05 20:04:40 +00:00
Colin LeMahieu 5e079577e1 [Hexagon] Adding round reg/imm and bitsplit instructions. 
llvm-svn: 225188
 2015-01-05 18:08:21 +00:00
Craig Topper d3c02f177a Replace several 'assert(false' with 'llvm_unreachable' or fold a condition into the assert. 
llvm-svn: 225160
 2015-01-05 10:15:49 +00:00
Colin LeMahieu 5691eb5ee7 Reverting 225045 and 225043 and XFAIL multiline.ll on hexagon 
llvm-svn: 225047
 2014-12-31 17:14:35 +00:00
Colin LeMahieu 79e8ebada2 [Hexagon] Removing assertion to appease buildbot until I can reproduce the problem 
llvm-svn: 225045
 2014-12-31 16:20:00 +00:00
Colin LeMahieu 94272611ac [Hexagon] Changing an llvm_unreachable to an assertion and returning 0. Relocations aren't implemented yet but we don't need to abort for this in release builds. 
llvm-svn: 225043
 2014-12-31 15:57:38 +00:00
Colin LeMahieu bc405294f0 [Hexagon] Adding accumulating add/sub, doubleword logic-not variants, doubleword bitfield extract, word parity, accumulating multiplies with saturation. 
llvm-svn: 225024
 2014-12-31 00:08:34 +00:00
Colin LeMahieu 8971e055ae [Hexagon] Adding double-logic on predicate instructions. 
llvm-svn: 225018
 2014-12-30 23:22:39 +00:00
Colin LeMahieu 65f3e12ed1 [Hexagon] Adding newvalue compare and jumps. 
llvm-svn: 225015
 2014-12-30 23:04:21 +00:00
Colin LeMahieu 0cba5f1b43 [Hexagon] Adding postincrement register newvalue stores. 
llvm-svn: 225010
 2014-12-30 22:34:08 +00:00
Colin LeMahieu 9014890819 [Hexagon] Removing old newvalue store variants. Adding postincrement immediate newvalue stores. 
llvm-svn: 225009
 2014-12-30 22:28:31 +00:00
Colin LeMahieu 820d5cb608 [Hexagon] Adding indexed store new-value variants. 
llvm-svn: 225007
 2014-12-30 22:00:26 +00:00
Colin LeMahieu 2bad4a7177 [Hexagon] Adding indexed store of immediates. 
llvm-svn: 225006
 2014-12-30 21:01:38 +00:00
Colin LeMahieu 94a498bf0e [Hexagon] Adding indexed stores. 
llvm-svn: 225005
 2014-12-30 20:42:23 +00:00
Colin LeMahieu 9161d47476 [Hexagon] Adding reg-reg indexed load forms. 
llvm-svn: 224997
 2014-12-30 18:58:47 +00:00
Colin LeMahieu 82fb8cba16 [Hexagon] Dropping old combine instructions without encodings. 
llvm-svn: 224992
 2014-12-30 17:53:54 +00:00
Colin LeMahieu 377ac65340 [Hexagon] Adding compare byte/halfword reg-reg/reg-imm forms. Adding compare to general register reg-imm form. 
llvm-svn: 224991
 2014-12-30 17:39:24 +00:00
Colin LeMahieu d7a56fd9ff [Hexagon] Updating constant extender def, adding alu-not instructions, compare to general register, and inverted compares. 
llvm-svn: 224989
 2014-12-30 15:44:17 +00:00
Colin LeMahieu 651b72095b [Hexagon] Adding allocframe, post-increment circular immediate stores, post-increment circular register stores, and bit reversed post-increment stores. 
llvm-svn: 224957
 2014-12-29 21:33:45 +00:00
Colin LeMahieu 488b6f7bbc [Hexagon] Fixing 224952 where an addressing mode update was missed. 
llvm-svn: 224955
 2014-12-29 21:18:02 +00:00
Colin LeMahieu bda31b42a0 [Hexagon] Adding post-increment register form stores and register-immediate form stores with tests. 
llvm-svn: 224952
 2014-12-29 20:44:51 +00:00
Colin LeMahieu 9a3cd3f58c [Hexagon] Replacing the remaining postincrement stores with versions that have encoding bits. 
llvm-svn: 224951
 2014-12-29 20:00:43 +00:00
Colin LeMahieu 3d34afb32d [Hexagon] Renaming old multiclass for removal. Adding post-increment store classes and instruction defs. 
llvm-svn: 224949
 2014-12-29 19:42:14 +00:00
Colin LeMahieu 8233fb002d [Hexagon] Adding auto-incrementing loads with and without byte reversal. 
llvm-svn: 224871
 2014-12-26 21:09:25 +00:00
Colin LeMahieu 0a721cd4e1 [Hexagon] Adding locked loads. 
llvm-svn: 224870
 2014-12-26 20:42:27 +00:00
Colin LeMahieu ff370ed90e [Hexagon] Adding deallocframe and circular addressing loads. 
llvm-svn: 224869
 2014-12-26 20:30:58 +00:00
Colin LeMahieu c83cbbf6a1 [Hexagon] Adding remaining post-increment instruction variants. Removing unused classes. 
llvm-svn: 224868
 2014-12-26 19:31:46 +00:00
Colin LeMahieu fe9612e09d [Hexagon] Adding post-increment unsigned byte loads. 
llvm-svn: 224867
 2014-12-26 19:12:11 +00:00
Colin LeMahieu 96976a10a3 [Hexagon] Adding post-increment signed byte loads with tests. 
llvm-svn: 224866
 2014-12-26 18:57:13 +00:00
Colin LeMahieu e193e1c48b [Hexagon] Removing old classes. 
llvm-svn: 224795
 2014-12-24 00:43:00 +00:00
Colin LeMahieu 947cd70413 [Hexagon] Adding doubleword load. 
llvm-svn: 224787
 2014-12-23 20:44:59 +00:00
Colin LeMahieu 026e88d317 [Hexagon] Reapplying 224775 load words. 
llvm-svn: 224786
 2014-12-23 20:02:16 +00:00
Colin LeMahieu 20be15718b Reverting 224775 until mayLoad flag is addressed. 
llvm-svn: 224783
 2014-12-23 19:22:59 +00:00
Colin LeMahieu 122aeaafea [Hexagon] Adding word loads. 
llvm-svn: 224775
 2014-12-23 18:06:56 +00:00
Colin LeMahieu 8e39cad934 [Hexagon] Adding signed halfword loads. 
llvm-svn: 224774
 2014-12-23 17:25:57 +00:00
Colin LeMahieu a9386d28a5 [Hexagon] Adding unsigned halfword load. 
llvm-svn: 224772
 2014-12-23 16:42:57 +00:00
Colin LeMahieu 4b1eac4dda [Hexagon] Adding memb instruction. Fixing whitespace in test from 224730. 
llvm-svn: 224735
 2014-12-22 21:40:43 +00:00
Colin LeMahieu af1e5de141 [Hexagon] Adding classes and load unsigned byte instruction, updating usages. 
llvm-svn: 224730
 2014-12-22 21:20:03 +00:00
Colin LeMahieu 0f850bde0e [Hexagon] Removing old variants of instructions and updating references. 
llvm-svn: 224612
 2014-12-19 20:29:29 +00:00
Colin LeMahieu 38ce8cd2e2 [Hexagon] Adding bit extraction and table indexing instructions. 
llvm-svn: 224610
 2014-12-19 20:01:08 +00:00
Colin LeMahieu 3c7f664d5a [Hexagon] Adding bit insertion instructions. 
llvm-svn: 224609
 2014-12-19 19:54:38 +00:00
Colin LeMahieu d63ef93b4b [Hexagon] Adding more xtype shift instructions. 
llvm-svn: 224608
 2014-12-19 19:51:35 +00:00
Colin LeMahieu cc09d1ccc5 [Hexagon] Adding xtype shift instructions. 
llvm-svn: 224604
 2014-12-19 19:34:50 +00:00
Colin LeMahieu f3db884efb [Hexagon] Adding transfers to and from control registers. 
llvm-svn: 224599
 2014-12-19 19:06:32 +00:00
Colin LeMahieu 402f772b82 [Hexagon] Adding doubleregs for control registers. Renaming control register class. 
llvm-svn: 224598
 2014-12-19 18:56:10 +00:00
Colin LeMahieu 5ccbb1298b [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
llvm-svn: 224556
 2014-12-19 00:06:53 +00:00
Colin LeMahieu 174476ed96 Reverting 224550, was not ready for commit. 
llvm-svn: 224552
 2014-12-18 23:36:15 +00:00
Colin LeMahieu 9000481cda [Hexagon] Adding loop0/1 sp0/1/2loop0 instructions. 
llvm-svn: 224550
 2014-12-18 23:27:51 +00:00
Colin LeMahieu 2055538edb [Hexagon] Reconfiguring register alternate names. 
llvm-svn: 224455
 2014-12-17 20:35:11 +00:00
Colin LeMahieu aa1bade7b4 [Hexagon] Updating doubleword shift usages to new versions. 
llvm-svn: 224391
 2014-12-16 23:36:15 +00:00
Colin LeMahieu 7fc90fc7e9 [Hexagon] Removing old XTYPE/BIT instructions and replacing usages. 
llvm-svn: 224381
 2014-12-16 22:17:09 +00:00
Colin LeMahieu f5acc8c625 [Hexagon] Adding tstbit/bitclr/bitset instructions. 
llvm-svn: 224374
 2014-12-16 21:28:58 +00:00
Colin LeMahieu 615757f2f1 [Hexagon] Adding bit count and twiddling instructions. 
llvm-svn: 224367
 2014-12-16 20:57:56 +00:00
Colin LeMahieu 6fce46baf6 [Hexagon] Adding asr/lsr/asl reg/imm, asl with saturation, asr with rounding. Doubleword abs/neg/not. Interleave and deinterleave instructions. 
llvm-svn: 224365
 2014-12-16 20:40:23 +00:00
Colin LeMahieu 1944a8cd04 [Hexagon] Adding absolute value, and negate with saturation 
llvm-svn: 224346
 2014-12-16 17:44:49 +00:00
Colin LeMahieu 455f24aa77 [Hexagon] Adding saturate and swizzle instructions. 
llvm-svn: 224343
 2014-12-16 16:27:17 +00:00
Colin LeMahieu d9b23509bf [Hexagon] Removing old multiply defs and updating references to new versions. 
llvm-svn: 224340
 2014-12-16 16:10:01 +00:00
Colin LeMahieu d9a00a9c38 [Hexagon] Adding doubleword multiplies with and without accumulation. 
llvm-svn: 224293
 2014-12-16 00:07:24 +00:00
Colin LeMahieu 18c927620a [Hexagon] Adding halfword to doubleword multiplies. 
llvm-svn: 224289
 2014-12-15 23:29:37 +00:00
Colin LeMahieu 64ffd52943 [Hexagon] Adding logical-logical accumulation instructions and tests. 
llvm-svn: 224288
 2014-12-15 23:19:07 +00:00
Colin LeMahieu 71e11a1d0d [Hexagon] Adding a number of additional multiply forms with tests. 
llvm-svn: 224282
 2014-12-15 22:10:37 +00:00
Colin LeMahieu 4a46429305 [Hexagon] Adding misc multiply encodings and tests. 
llvm-svn: 224273
 2014-12-15 21:17:03 +00:00
Colin LeMahieu 26f884aedf [Hexagon] Adding doubleworld accumulating multiplies of halfwords. 
llvm-svn: 224267
 2014-12-15 20:17:46 +00:00
Colin LeMahieu 572c53e258 [Hexagon] Adding accumulating half word multiplies. 
llvm-svn: 224266
 2014-12-15 20:10:28 +00:00
Colin LeMahieu d1704cdc07 [Hexagon] Adding multiply with rnd/sat/rndsat 
llvm-svn: 224265
 2014-12-15 20:01:59 +00:00
Colin LeMahieu fe4012a969 [Hexagon] Adding encoding bits for halfword multiplies. 
llvm-svn: 224261
 2014-12-15 19:22:07 +00:00
Colin LeMahieu 90482a77b1 [Hexagon] Adding double word add/min/minu/max/maxu instructions and tests. 
llvm-svn: 224153
 2014-12-12 21:29:25 +00:00
Colin LeMahieu 984ef17d66 [Hexagon] Adding J class call instructions. 
llvm-svn: 224150
 2014-12-12 21:12:27 +00:00
Matthias Braun 7e37a5f523 [CodeGen] Add print and verify pass after each MachineFunctionPass by default 
Previously print+verify passes were added in a very unsystematic way, which is
annoying when debugging as you miss intermediate steps and allows bugs to stay
unnotice when no verification is performed.

To make this change practical I added the possibility to explicitely disable
verification. I used this option on all places where no verification was
performed previously (because alot of places actually don't pass the
MachineVerifier).
In the long term these problems should be fixed properly and verification
enabled after each pass. I'll enable some more verification in subsequent
commits.

This is the 2nd attempt at this after realizing that PassManager::add() may
actually delete the pass.

llvm-svn: 224059
 2014-12-11 21:26:47 +00:00
Rafael Espindola 01c73610d0 This reverts commit r224043 and r224042. 
check-llvm was failing.

llvm-svn: 224045
 2014-12-11 20:03:57 +00:00
Matthias Braun a7c82a9f1d [CodeGen] Add print and verify pass after each MachineFunctionPass by default 
Previously print+verify passes were added in a very unsystematic way, which is
annoying when debugging as you miss intermediate steps and allows bugs to stay
unnotice when no verification is performed.

To make this change practical I added the possibility to explicitely disable
verification. I used this option on all places where no verification was
performed previously (because alot of places actually don't pass the
MachineVerifier).
In the long term these problems should be fixed properly and verification
enabled after each pass. I'll enable some more verification in subsequent
commits.

llvm-svn: 224042
 2014-12-11 19:42:05 +00:00
Colin LeMahieu 150b6b3a73 [Hexagon] Renaming classes in preparation for replacement. 
llvm-svn: 224036
 2014-12-11 19:01:28 +00:00
Colin LeMahieu adab80720d [Hexagon] Ading i64 <- i32, i32 sextw pattern. 
llvm-svn: 224027
 2014-12-11 17:08:21 +00:00
Colin LeMahieu eb52f69f59 [Hexagon] Adding encoding information for sign extend word instruction. 
llvm-svn: 224026
 2014-12-11 16:43:06 +00:00
Colin LeMahieu 220adb6370 [Hexagon] Adding combine ri/ir instructions. 
llvm-svn: 223971
 2014-12-10 22:23:07 +00:00
Colin LeMahieu db0b13cef0 [Hexagon] Adding encodings for JR class instructions. Updating complier usages. 
llvm-svn: 223967
 2014-12-10 21:24:10 +00:00
Colin LeMahieu 8872d20788 [Hexagon] Adding JR class predicated call reg instructions. 
llvm-svn: 223933
 2014-12-10 18:24:16 +00:00
Colin LeMahieu b32bf14c2a [Hexagon] [NFC] Cleaning up unused classes. 
llvm-svn: 223845
 2014-12-09 22:33:26 +00:00
Colin LeMahieu b030c254c0 [Hexagon] Fixing broken tests. 
llvm-svn: 223823
 2014-12-09 20:36:53 +00:00
Colin LeMahieu 4af437fee5 [Hexagon] Updating rr/ri 32/64 transfer encodings and adding tests. 
llvm-svn: 223821
 2014-12-09 20:23:30 +00:00
Colin LeMahieu b580d7d8c8 [Hexagon] Adding word combine dot-new form and replacing old combine opcode. 
llvm-svn: 223815
 2014-12-09 19:23:45 +00:00
Colin LeMahieu 30dcb232b0 [Hexagon] Updating predicate register transfers and adding tstbit to allow select selection. Updating ll tests with predicate transfers that previously had nop encodings. 
llvm-svn: 223800
 2014-12-09 18:16:49 +00:00
Colin LeMahieu 5cf5632696 [Hexagon] Removing old def versions and replacing usages with versions that have encodings. 
llvm-svn: 223720
 2014-12-08 23:55:43 +00:00
Colin LeMahieu f5b4d655d2 [Hexagon] Adding any8, all8, and/or/xor/andn/orn/not predicate register forms, mask, and vitpack instructions and patterns. 
llvm-svn: 223710
 2014-12-08 23:07:59 +00:00
Colin LeMahieu b6c4dd96f9 [Hexagon] Adding xtype doubleword add, sub, and, or, xor and patterns. 
llvm-svn: 223702
 2014-12-08 22:19:14 +00:00
Colin LeMahieu 9bfe5473da [Hexagon] Adding xtype doubleword comparisons. Removing unused multiclass. 
llvm-svn: 223701
 2014-12-08 21:56:47 +00:00
Colin LeMahieu 025f860638 [Hexagon] Adding xtype parity, min, minu, max, maxu instructions. 
llvm-svn: 223693
 2014-12-08 21:19:18 +00:00
Colin LeMahieu 8d1376c60e [Hexagon] Adding xtype halfword add/sub ll/hl/lh/hh/sat/<<16 instructions. 
llvm-svn: 223692
 2014-12-08 20:33:01 +00:00
Colin LeMahieu cc46cd8eec [Hexagon] Adding add/sub with saturation. Removing unused def. Cleaning up shift patterns. 
llvm-svn: 223680
 2014-12-08 18:33:49 +00:00
Colin LeMahieu b56e6cd9b9 [Hexagon] Adding combine reg, reg with predicated forms. 
llvm-svn: 223667
 2014-12-08 17:33:06 +00:00
Colin LeMahieu a55070dbdd [Hexagon] Adding packhl instruction. 
llvm-svn: 223664
 2014-12-08 17:01:18 +00:00
Colin LeMahieu d8b766072b [Hexagon] Relocating logical instructions and templates later in the td file. 
llvm-svn: 223523
 2014-12-05 21:51:12 +00:00
Colin LeMahieu 2c77a35e6e [Hexagon] Adding sub/and/or reg, imm forms 
llvm-svn: 223522
 2014-12-05 21:38:29 +00:00
Colin LeMahieu 9665f98c10 [Hexagon] Updating mux_ir/ri/ii/rr with encoding bits 
llvm-svn: 223515
 2014-12-05 21:09:27 +00:00
Colin LeMahieu 19985e9a8d [Hexagon] Adding tfrih/l instructions. 
llvm-svn: 223506
 2014-12-05 20:07:19 +00:00
Colin LeMahieu a4ab58101a [Hexagon] Adding add reg, imm form with encoding bits and test. 
llvm-svn: 223504
 2014-12-05 19:51:23 +00:00
Colin LeMahieu 383c36e3a8 [Hexagon] Adding DoubleRegs decoder. Moving C2_mux and A2_nop. Adding combine imm-imm form. 
llvm-svn: 223494
 2014-12-05 18:24:06 +00:00
Colin LeMahieu 63035ebee1 [Hexagon] [NFC] Rearranging patterns and mux instruction. 
llvm-svn: 223488
 2014-12-05 17:58:06 +00:00
Colin LeMahieu 7358593e34 [Hexagon] [NFC] Rearranging def order. 
llvm-svn: 223487
 2014-12-05 17:55:51 +00:00
Colin LeMahieu 7f0a430c7d [Hexagon] Adding combine reg-reg forms. 
llvm-svn: 223485
 2014-12-05 17:38:36 +00:00
Colin LeMahieu 01785bb063 [Hexagon] Marking several instructions as isCodeGenOnly=0 and adding direct disassembly tests for many instructions. 
llvm-svn: 223482
 2014-12-05 17:27:39 +00:00
Colin LeMahieu 5d6f03bd5a [Hexagon] Marking some instructions as CodeGenOnly=0 and adding disassembly tests. 
llvm-svn: 223334
 2014-12-04 03:41:21 +00:00
NAKAMURA Takumi 597fbb5230 HexagonMCInst.h: Qualify constants explicitly to appease msc17. 
llvm-svn: 223325
 2014-12-04 00:26:39 +00:00
Colin LeMahieu 654f2d2037 [Hexagon] Converting member InstrDesc to static variable. 
llvm-svn: 223268
 2014-12-03 21:40:25 +00:00
Colin LeMahieu 7e9908ea10 [Hexagon] Converting subclass members to an implicit operand. 
llvm-svn: 223264
 2014-12-03 20:23:22 +00:00
Colin LeMahieu 089791db48 [NFC] Fixing pendantic warning extra semicolons. 
llvm-svn: 223246
 2014-12-03 17:36:39 +00:00
Colin LeMahieu 1d04fa411f [Hexagon] [NFC] Moving function implementations out of header. Clang-formatting files. 
llvm-svn: 223245
 2014-12-03 17:35:39 +00:00
Colin LeMahieu b4e5be4c66 [Hexagon] [NFC] Renaming *packetStart to *packetBegin 
llvm-svn: 223243
 2014-12-03 17:31:43 +00:00