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5 Commits

Author SHA1 Message Date
David Blaikie a79ac14fa6 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction 
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
 2015-02-27 21:17:42 +00:00
Elena Demikhovsky 8e8fde8e93 AVX-512: changes in intrinsics 
1) Changed gather and scatter intrinsics. Now they are aligned with GCC built-ins. There is no more non-masked form. Masked intrinsic receives -1 if all lanes are executed.
2) I changed the function that works with intrinsics inside X86ISelLowering.cpp. I put all intrinsics in one table. I did it for INTRINSICS_W_CHAIN and plan to put all intrinsics from WO_CHAIN set to the same table in order to avoid the long-long "switch". (I wanted to use static map initialization that allowed by C++11 but I wasn't able to compile it on VS2012).
3) I added gather/scatter prefetch intrinsics.
4) I fixed MRMm encoding for masked instructions.

llvm-svn: 208522
 2014-05-12 07:18:51 +00:00
Cameron McInally 4532596b8f Fix AVX512 Gather and Scatter execution domains. 
llvm-svn: 204804
 2014-03-26 13:50:50 +00:00
Elena Demikhovsky 534015e550 AVX-512: gather-scatter tests; added foldable instructions; 
Specify GATHER/SCATTER as heavy instructions.

llvm-svn: 189736
 2013-09-02 07:12:29 +00:00
Elena Demikhovsky 4def4b088f AVX-512: Added GATHER and SCATTER instructions. 
llvm-svn: 189729
 2013-09-01 14:24:41 +00:00