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14122 Commits

Author SHA1 Message Date
Evan Cheng 7d693898ee Add pseudo dependency to force a def&use operand to be scheduled last (unless 
the distance between the def and another use is much longer). This is under
option control for now "-sched-lower-defnuse".

llvm-svn: 28201
 2006-05-09 07:13:34 +00:00
Evan Cheng 2c74848af1 Debugging info 
llvm-svn: 28200
 2006-05-09 06:55:15 +00:00
Evan Cheng fc532fe1b7 Remove a completed entry. 
llvm-svn: 28199
 2006-05-09 06:54:05 +00:00
Evan Cheng ae45020720 PR 770 - permit coallescing of registers in subset register classes. 
llvm-svn: 28197
 2006-05-09 06:37:48 +00:00
Chris Lattner 4ebc6a2311 Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code. 
llvm-svn: 28194
 2006-05-09 05:33:48 +00:00
Chris Lattner 8c2bfc0659 Oh yeah, there are two of these now, unify both. 
llvm-svn: 28192
 2006-05-09 05:24:50 +00:00
Chris Lattner 6341df8069 Setting SwitchToSectionDirective properly in the MASM backend permits a bunch 
of code to be unified.

llvm-svn: 28191
 2006-05-09 05:23:12 +00:00
Chris Lattner 0b7acaf027 MASM doesn't have one of these. 
llvm-svn: 28190
 2006-05-09 05:21:47 +00:00
Chris Lattner d36cc2b610 Don't prefix section directives with a tab. Doing so causes blank lines to 
be emitted to the .s file.

llvm-svn: 28189
 2006-05-09 05:19:59 +00:00
Chris Lattner e64f764d25 Make the masm codepath work like the normal code path. 
llvm-svn: 28188
 2006-05-09 05:15:58 +00:00
Chris Lattner e0006c6794 Preserve prior behavior 
llvm-svn: 28187
 2006-05-09 05:15:24 +00:00
Chris Lattner c0f0dfa56f The MASM asmprinter has been fixed, these hacks are no longer needed. 
llvm-svn: 28186
 2006-05-09 05:13:34 +00:00
Chris Lattner d0201946ad Fix the MASM asmprinter's lies. It does not want to emit code to .text/.data 
it wants it emitted to _text/_data.

llvm-svn: 28185
 2006-05-09 05:12:53 +00:00
Chris Lattner 8488ba2e41 Split SwitchSection into SwitchTo{Text|Data}Section methods. 
llvm-svn: 28184
 2006-05-09 04:59:56 +00:00
Chris Lattner 8587f8885d Some notes and thoughts to myself 
llvm-svn: 28182
 2006-05-09 04:58:46 +00:00
Chris Lattner 4fe87d67c4 Patch to make some xforms preserve each other. Patch contributed by 
Domagoj Babic!

llvm-svn: 28181
 2006-05-09 04:13:41 +00:00
Chris Lattner 6d8dd189f6 Move some methods out of line so that MutexGuard.h isn't needed in a public header. 
llvm-svn: 28179
 2006-05-08 22:00:52 +00:00
Chris Lattner aa193d80a9 Another bad case I noticed 
llvm-svn: 28177
 2006-05-08 21:39:45 +00:00
Chris Lattner 5bcea612f4 add a note 
llvm-svn: 28176
 2006-05-08 21:24:21 +00:00
Chris Lattner 446e1ef26a Make the case I just checked in stronger. Now we compile this: 
short test2(short X, short x) {
  int Y = (short)(X+x);
  return Y >> 1;
}

to:

_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r3, r2, 1
        blr

instead of:

_test2:
        add r2, r3, r4
        extsh r2, r2
        srwi r2, r2, 1
        extsh r3, r2
        blr

llvm-svn: 28175
 2006-05-08 21:18:59 +00:00
Chris Lattner 29062da0ac Implement and_sext.ll:test3, generating: 
_test4:
        srawi r3, r3, 16
        blr

instead of:

_test4:
        srwi r2, r3, 16
        extsh r3, r2
        blr

for:

short test4(unsigned X) {
  return (X >> 16);
}

llvm-svn: 28174
 2006-05-08 20:59:41 +00:00
Nate Begeman ce6646c366 Yet more readme updating 
llvm-svn: 28172
 2006-05-08 20:54:02 +00:00
Chris Lattner 2935d8190c Compile this: 
short test4(unsigned X) {
  return (X >> 16);
}

to:

_test4:
        movl 4(%esp), %eax
        sarl $16, %eax
        ret

instead of:

_test4:
        movl $-65536, %eax
        andl 4(%esp), %eax
        sarl $16, %eax
        ret

llvm-svn: 28171
 2006-05-08 20:51:54 +00:00
Nate Begeman 68a45419cc New note about something bad happening in target independent optimizers 
llvm-svn: 28170
 2006-05-08 20:08:28 +00:00
Nate Begeman 0eb8f2e496 Proving once again that I am not as smart as the compiler 
llvm-svn: 28169
 2006-05-08 19:09:24 +00:00
Nate Begeman 9b6d4c2968 Fold more shifts into inserts, and update the README 
llvm-svn: 28168
 2006-05-08 17:38:32 +00:00
Chris Lattner 78da6792e7 Fold shifts with undef operands. 
llvm-svn: 28167
 2006-05-08 17:29:49 +00:00
Chris Lattner 10c653744e When tracking demanded bits, if any bits from the sext of an SRA are demanded, 
then so is the input sign bit.  This fixes mediabench/g721 on X86.

llvm-svn: 28166
 2006-05-08 17:22:53 +00:00
Nate Begeman d7a19102d1 Make emission of jump tables a bit less conservative; they are now required 
to be only 31.25% dense, rather than 75% dense.

llvm-svn: 28165
 2006-05-08 16:51:36 +00:00
Evan Cheng 9733bde74c Fixing truncate. Previously we were emitting truncate from r16 to r8 as 
movw. That is we promote the destination operand to r16. So
        %CH = TRUNC_R16_R8 %BP
is emitted as
        movw %bp, %cx.

This is incorrect. If %cl is live, it would be clobbered.
Ideally we want to do the opposite, that is emitted it as
        movb ??, %ch
But this is not possible since %bp does not have a r8 sub-register.

We are now defining a new register class R16_ which is a subclass of R16
containing only those 16-bit registers that have r8 sub-registers (i.e.
AX - DX). We isel the truncate to two instructions, a MOV16to16_ to copy the
value to the R16_ class, followed by a TRUNC_R16_R8.

Due to bug 770, the register colaescer is not going to coalesce between R16 and
R16_. That will be fixed later so we can eliminate the MOV16to16_. Right now, it
can only be eliminated if we are lucky that source and destination registers are
the same.

llvm-svn: 28164
 2006-05-08 08:01:26 +00:00
Nate Begeman dc996b3f6c Update some stuff now that the new rlwimi code has gone in 
llvm-svn: 28162
 2006-05-08 02:52:38 +00:00
Nate Begeman e5ce5bb6da Fix PR772 
llvm-svn: 28161
 2006-05-08 01:35:01 +00:00
Evan Cheng 6732dcd5b3 Typo's 
llvm-svn: 28158
 2006-05-07 10:10:20 +00:00
Jeff Cohen 04196acdcb Unlike Unix, Windows won't let a file be implicitly replaced via renaming without explicit permission. 
llvm-svn: 28157
 2006-05-07 02:51:51 +00:00
Nate Begeman 1333cead5b New rlwimi implementation, which is superior to the old one. There are 
still a couple missed optimizations, but we now generate all the possible
rlwimis for multiple inserts into the same bitfield.  More regression tests
to come.

llvm-svn: 28156
 2006-05-07 00:23:38 +00:00
Chris Lattner cd4a643728 Use ComputeMaskedBits to determine # sign bits as a fallback. This allows us 
to handle all kinds of stuff, including silly things like:
sextinreg(setcc,i16) -> setcc.

llvm-svn: 28155
 2006-05-06 23:48:13 +00:00
Chris Lattner 4f3de3e33c Add some more sign propagation cases 
llvm-svn: 28154
 2006-05-06 23:40:29 +00:00
Jeff Cohen 9978476c14 Apply bug fix supplied by Greg Pettyjohn for a bug he found: '<invalid>' is not a legal path on Windows. 
llvm-svn: 28153
 2006-05-06 23:25:53 +00:00
Chris Lattner 7e7bcf3a54 Simplify some code, add a couple minor missed folds 
llvm-svn: 28152
 2006-05-06 23:06:26 +00:00
Chris Lattner 751817c54f constant fold sign_extend_inreg 
llvm-svn: 28151
 2006-05-06 23:05:41 +00:00
Chris Lattner 2a4d7b845b remove cases handled elsewhere 
llvm-svn: 28150
 2006-05-06 22:43:44 +00:00
Chris Lattner f86075731d Add some more simple sign bit propagation cases. 
llvm-svn: 28149
 2006-05-06 22:39:59 +00:00
Jeff Cohen ce9b9fe6eb Fix some loose ends in MASM support. 
llvm-svn: 28148
 2006-05-06 21:27:14 +00:00
Chris Lattner 1ecb2a2dac Use the new TargetLowering::ComputeNumSignBits method to eliminate 
sign_extend_inreg operations.  Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:

short test(short X, short x) {
  int Y = X+x;
  return (Y >> 1);
}
short test2(short X, short x) {
  int Y = (short)(X+x);
  return Y >> 1;
}

into:

_test:
        add r2, r3, r4
        srawi r3, r2, 1
        blr
_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r3, r2, 1
        blr

instead of:

_test:
        add r2, r3, r4
        srawi r2, r2, 1
        extsh r3, r2
        blr
_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r2, r2, 1
        extsh r3, r2
        blr

llvm-svn: 28146
 2006-05-06 09:30:03 +00:00
Chris Lattner 7206d74f0c Add some really really simple code for computing sign-bit propagation. 
This will certainly be enhanced in the future.

llvm-svn: 28145
 2006-05-06 09:27:13 +00:00
Chris Lattner 21cd99024a When inserting casts, be careful of where we put them. We cannot insert 
a cast immediately before a PHI node.

This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll

llvm-svn: 28143
 2006-05-06 09:10:37 +00:00
Chris Lattner 1d441adfbf Move some code around. 
Make the "fold (and (cast A), (cast B)) -> (cast (and A, B))" transformation
only apply when both casts really will cause code to be generated.  If one or
both doesn't, then this xform doesn't remove a cast.

This fixes Transforms/InstCombine/2006-05-06-Infloop.ll

llvm-svn: 28141
 2006-05-06 09:00:16 +00:00
Chris Lattner 6d4a2dc4ad Teach the X86 backend about non-i32 inline asm register classes. 
llvm-svn: 28139
 2006-05-06 00:29:37 +00:00
Chris Lattner 86a1467fc0 Fold (trunc (srl x, c)) -> (srl (trunc x), c) 
llvm-svn: 28138
 2006-05-06 00:11:52 +00:00
Chris Lattner 907e392dba Fold trunc(any_ext). This gives stuff like: 
27,28c27
<       movzwl %di, %edi
<       movl %edi, %ebx
---
>       movw %di, %bx

llvm-svn: 28137
 2006-05-05 22:56:26 +00:00
Chris Lattner 57f8c5a387 Shrink shifts when possible. 
llvm-svn: 28136
 2006-05-05 22:53:17 +00:00
Chris Lattner 0f64932a5c Implement ComputeMaskedBits/SimplifyDemandedBits for ISD::TRUNCATE 
llvm-svn: 28135
 2006-05-05 22:32:12 +00:00
Chris Lattner 8b9e11c110 Print a grouping around inline asm blocks so that we can tell when we are 
using them.

llvm-svn: 28134
 2006-05-05 21:50:04 +00:00
Chris Lattner c22d4bede5 Print *some* grouping around inline asm blocks so we know where they are. 
llvm-svn: 28133
 2006-05-05 21:48:50 +00:00
Chris Lattner a633c31319 Indent multiline asm strings more nicely 
llvm-svn: 28132
 2006-05-05 21:47:05 +00:00
Chris Lattner 44a73e9fa5 Teach the code generator to use cvtss2sd as extload f32 -> f64 
llvm-svn: 28131
 2006-05-05 21:35:18 +00:00
Chris Lattner 3d26577396 Fold (fpext (load x)) -> (extload x) 
llvm-svn: 28130
 2006-05-05 21:34:35 +00:00
Chris Lattner 3e3f2c63c3 More aggressively sink GEP offsets into loops. For example, before we 
generated:

        movl 8(%esp), %eax
        movl %eax, %edx
        addl $4316, %edx
        cmpb $1, %cl
        ja LBB1_2       #cond_false
LBB1_1: #cond_true
        movl L_QuantizationTables720$non_lazy_ptr, %ecx
        movl %ecx, (%edx)
        movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
        movl %edx, 4460(%eax)
        ret
...

Now we generate:

        movl 8(%esp), %eax
        cmpb $1, %cl
        ja LBB1_2       #cond_false
LBB1_1: #cond_true
        movl L_QuantizationTables720$non_lazy_ptr, %ecx
        movl %ecx, 4316(%eax)
        movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
        movl %ecx, 4460(%eax)
        ret

... which uses one fewer register.

llvm-svn: 28129
 2006-05-05 21:17:49 +00:00
Chris Lattner e745c7de0e Fix an infinite loop compiling oggenc last night. 
llvm-svn: 28128
 2006-05-05 20:51:30 +00:00
Evan Cheng 52c22512b9 Need extload patterns after Chris' DAG combiner changes 
llvm-svn: 28127
 2006-05-05 08:23:07 +00:00
Chris Lattner 3af1053488 Implement InstCombine/cast.ll:test29 
llvm-svn: 28126
 2006-05-05 06:39:07 +00:00
Chris Lattner 25a5283a86 Fold some common code. 
llvm-svn: 28124
 2006-05-05 06:32:04 +00:00
Chris Lattner 002ee91457 Implement: 
// fold (and (sext x), (sext y)) -> (sext (and x, y))
  // fold (or  (sext x), (sext y)) -> (sext (or  x, y))
  // fold (xor (sext x), (sext y)) -> (sext (xor x, y))
  // fold (and (aext x), (aext y)) -> (aext (and x, y))
  // fold (or  (aext x), (aext y)) -> (aext (or  x, y))
  // fold (xor (aext x), (aext y)) -> (aext (xor x, y))

llvm-svn: 28123
 2006-05-05 06:31:05 +00:00
Chris Lattner 5ac4293606 Pull and through and/or/xor. This compiles some bitfield code to: 
mov EAX, DWORD PTR [ESP + 4]
        mov ECX, DWORD PTR [EAX]
        mov EDX, ECX
        add EDX, EDX
        or EDX, ECX
        and EDX, -2147483648
        and ECX, 2147483647
        or EDX, ECX
        mov DWORD PTR [EAX], EDX
        ret

instead of:

        sub ESP, 4
        mov DWORD PTR [ESP], ESI
        mov EAX, DWORD PTR [ESP + 8]
        mov ECX, DWORD PTR [EAX]
        mov EDX, ECX
        add EDX, EDX
        mov ESI, ECX
        and ESI, -2147483648
        and EDX, -2147483648
        or EDX, ESI
        and ECX, 2147483647
        or EDX, ECX
        mov DWORD PTR [EAX], EDX
        mov ESI, DWORD PTR [ESP]
        add ESP, 4
        ret

llvm-svn: 28122
 2006-05-05 06:10:43 +00:00
Chris Lattner 812646aa0c Implement a variety of simplifications for ANY_EXTEND. 
llvm-svn: 28121
 2006-05-05 05:58:59 +00:00
Chris Lattner 8d6fc20181 Factor some code, add these transformations: 
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
  // fold (or  (trunc x), (trunc y)) -> (trunc (or  x, y))
  // fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))

llvm-svn: 28120
 2006-05-05 05:51:50 +00:00
Evan Cheng ddb6cc1d8e Better implementation of truncate. ISel matches it to a pseudo instruction 
that gets emitted as movl (for r32 to i16, i8) or a movw (for r16 to i8). And
if the destination gets allocated a subregister of the source operand, then
the instruction will not be emitted at all.

llvm-svn: 28119
 2006-05-05 05:40:20 +00:00
Chris Lattner 304bbf3b1d New note, Nate, please check to see if I'm full of it :) 
llvm-svn: 28118
 2006-05-05 05:36:15 +00:00
Jeff Cohen 78a7f0e05e Fix VC++ compilation error. 
llvm-svn: 28117
 2006-05-05 01:47:05 +00:00
Chris Lattner 7a3ecf7993 Sink noop copies into the basic block that uses them. This reduces the number 
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.

This reduces the load on the coallescer and register allocator.  For example
on a codec on X86, we went from:

   1643 asm-printer           - Number of machine instrs printed
    419 liveintervals         - Number of loads/stores folded into instructions
   1144 liveintervals         - Number of identity moves eliminated after coalescing
   1022 liveintervals         - Number of interval joins performed
    282 liveintervals         - Number of intervals after coalescing
   1304 liveintervals         - Number of original intervals
     86 regalloc              - Number of times we had to backtrack
1.90232 regalloc              - Ratio of intervals processed over total intervals
     40 spiller               - Number of values reused
    182 spiller               - Number of loads added
    121 spiller               - Number of stores added
    132 spiller               - Number of register spills
      6 twoaddressinstruction - Number of instructions commuted to coalesce
    360 twoaddressinstruction - Number of two-address instructions

to:

   1636 asm-printer           - Number of machine instrs printed
    403 liveintervals         - Number of loads/stores folded into instructions
   1155 liveintervals         - Number of identity moves eliminated after coalescing
   1033 liveintervals         - Number of interval joins performed
    279 liveintervals         - Number of intervals after coalescing
   1312 liveintervals         - Number of original intervals
     76 regalloc              - Number of times we had to backtrack
1.88998 regalloc              - Ratio of intervals processed over total intervals
      1 spiller               - Number of copies elided
     41 spiller               - Number of values reused
    191 spiller               - Number of loads added
    114 spiller               - Number of stores added
    128 spiller               - Number of register spills
      4 twoaddressinstruction - Number of instructions commuted to coalesce
    356 twoaddressinstruction - Number of two-address instructions

On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted.  It increases the number
of register coallesces.

llvm-svn: 28115
 2006-05-05 01:04:50 +00:00
Chris Lattner b6277c510c Adjust to use proper TargetData copy ctor 
llvm-svn: 28112
 2006-05-04 21:18:40 +00:00
Chris Lattner abdf4d569c Final pass of minor cleanups for MachineInstr 
llvm-svn: 28110
 2006-05-04 19:36:09 +00:00
Evan Cheng 9add880566 Initial support for register pressure aware scheduling. The register reduction 
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.

llvm-svn: 28108
 2006-05-04 19:16:39 +00:00
Chris Lattner 53af9da363 Remove redundancy and a level of indirection when creating machine operands 
llvm-svn: 28107
 2006-05-04 19:14:44 +00:00
Chris Lattner 469647bf38 Remove and simplify some more machineinstr/machineoperand stuff. 
llvm-svn: 28105
 2006-05-04 18:16:01 +00:00
Chris Lattner 10b71c0d08 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. 
llvm-svn: 28104
 2006-05-04 18:05:43 +00:00
Chris Lattner 10d6341618 Move some methods out of MachineInstr into MachineOperand 
llvm-svn: 28102
 2006-05-04 17:52:23 +00:00
Chris Lattner fb29692055 Fix Transforms/InstCombine/2006-05-04-DemandedBitCrash.ll 
llvm-svn: 28101
 2006-05-04 17:33:35 +00:00
Chris Lattner fef7a2d0f5 There shalt be only one "immediate" operand type! 
llvm-svn: 28099
 2006-05-04 17:21:20 +00:00
Chris Lattner 15c52bda1d Change "value" in MachineOperand to be a GlobalValue, as that is the only 
thing that can be in it.  Remove a dead method.

llvm-svn: 28098
 2006-05-04 17:02:51 +00:00
Chris Lattner 13d5f3eb05 Revert Nate's CR patch from last night, which caused many regressions (e.g. fhourstones). 
Loading and storing off R0 isn't what we wanted.  Also, taking some CR's out of
CRRC seems to cause failures as well.  Further investigation is required.

llvm-svn: 28097
 2006-05-04 16:56:45 +00:00
Jeff Cohen 06041abeb6 Make external globals public; other minor cleanup. 
llvm-svn: 28096
 2006-05-04 16:20:22 +00:00
Jeff Cohen f812a4fa75 Make Intel syntax the default when LLVM is built with VC++. 
llvm-svn: 28095
 2006-05-04 16:19:27 +00:00
Chris Lattner ee64b6b40f Remove a bunch more dead V9 specific stuff 
llvm-svn: 28094
 2006-05-04 01:26:39 +00:00
Chris Lattner 940cc978ef Remove a bunch more SparcV9 specific stuff 
llvm-svn: 28093
 2006-05-04 01:15:02 +00:00
Chris Lattner 6e663f1c1e Remove some more V9-specific stuff. 
llvm-svn: 28092
 2006-05-04 00:49:59 +00:00
Chris Lattner 9f6639b64d Remove some more unused stuff from MachineInstr that was leftover from V9. 
llvm-svn: 28091
 2006-05-04 00:44:25 +00:00
Chris Lattner 2aef59f123 Simplify handling of relocations 
llvm-svn: 28090
 2006-05-04 00:42:08 +00:00
Evan Cheng 8b1cde2bbe Use movsd to shuffle in the lowest two elements of a v4f32 / v4i32 vector when 
movlps cannot be used (e.g. when load from m64 has multiple uses).

llvm-svn: 28089
 2006-05-03 20:32:03 +00:00
Chris Lattner e3a9c70ba0 Change from using MachineRelocation ctors to using static methods 
in MachineRelocation to create Relocations.

llvm-svn: 28088
 2006-05-03 20:30:20 +00:00
Chris Lattner 005d7174c8 minor cleanups, no functionality change 
llvm-svn: 28087
 2006-05-03 18:55:56 +00:00
Chris Lattner 9e68942d78 inline a simple method 
llvm-svn: 28083
 2006-05-03 17:21:32 +00:00
Chris Lattner 1d8ee1fc80 Suck block address tracking out of targets into the JIT Emitter. This 
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.

llvm-svn: 28082
 2006-05-03 17:10:41 +00:00
Chris Lattner 9954bc9c19 Fix a bug in Owen's checkin that broke the CBE on all non sparc v9 platforms. 
llvm-svn: 28081
 2006-05-03 05:48:41 +00:00
Nate Begeman 43b1ed7e3d Teach the x86 jit how to handle jump tables not directly used by a jump 
instruction.

llvm-svn: 28080
 2006-05-03 04:52:47 +00:00
Nate Begeman df4883971e Finish up the initial jump table implementation by allowing jump tables to 
not be 100% dense.  Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.

llvm-svn: 28079
 2006-05-03 03:48:02 +00:00
Evan Cheng ffef8b9412 Bottom up register pressure reduction work: clean up some hacks and enhanced 
the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)

llvm-svn: 28076
 2006-05-03 02:10:45 +00:00
Owen Anderson 20a631fde7 Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. 
This fixes PR 759.

llvm-svn: 28074
 2006-05-03 01:29:57 +00:00
Chris Lattner 37c39b9c62 Align function bodies correctly. 
llvm-svn: 28073
 2006-05-03 01:03:20 +00:00
Chris Lattner 77fe5b4459 Simplify some code. Don't add memory blocks to the Blocks list twice. 
llvm-svn: 28071
 2006-05-03 00:54:49 +00:00
Chris Lattner 667a056e11 Add assertions that verify that the actual arguments to a call or invoke match 
the prototype of the called function.

llvm-svn: 28070
 2006-05-03 00:48:22 +00:00
Chris Lattner d8b192ba3b Change the BasicBlockAddrs map to be a vector, indexed by MBB number. 
llvm-svn: 28069
 2006-05-03 00:32:55 +00:00
Chris Lattner 0267807ddc Keep the alpha JIT similar to the PPC/X86 jits 
llvm-svn: 28068
 2006-05-03 00:31:21 +00:00
Chris Lattner 0574e47dca Simplify some code 
llvm-svn: 28066
 2006-05-03 00:13:06 +00:00
Chris Lattner b8065a9a3a Several related changes: 
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
   from the MachineCodeEmitter interface, and reducing the amount of target-
   specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
   *right* next to the functions that they belong to, instead of in a separate
   pool of memory.  This makes all memory for a function be contiguous, and
   means the JITEmitter only tracks one block of memory now.

llvm-svn: 28065
 2006-05-02 23:22:24 +00:00
Nate Begeman 233391f5f5 Remove some stuff from the README 
llvm-svn: 28063
 2006-05-02 22:43:31 +00:00
Chris Lattner 23621fe8f4 Do not make the JIT memory manager manage the memory for globals. Instead 
just have the JIT malloc them.

llvm-svn: 28062
 2006-05-02 21:57:51 +00:00
Chris Lattner 25b95ed868 Minor cleanups, no functionality change. 
llvm-svn: 28061
 2006-05-02 21:44:14 +00:00
Chris Lattner e1c96369e2 Fix a purely hypothetical problem (for now): emitWord emits in the host 
byte format.  This doesn't work when using the code emitter in a cross target
environment.  Since the code emitter is only really used by the JIT, this
isn't a current problem, but if we ever start emitting .o files, it would be.

llvm-svn: 28060
 2006-05-02 19:14:47 +00:00
Chris Lattner c9aa3715e8 Refactor the machine code emitter interface to pull the pointers for the current 
code emission location into the base class, instead of being in the derived classes.

This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments.  This implements feature request #1 of PR469.

llvm-svn: 28059
 2006-05-02 18:27:26 +00:00
Nate Begeman bbcbf48aab Since we don't handle callee-save CRs right yet, don't allocate them. Also 
don't step on R11 in the middle of a function when saving and restoring CRs

llvm-svn: 28058
 2006-05-02 17:37:31 +00:00
Nate Begeman 4971ba5f41 Print function number instead of name 
llvm-svn: 28057
 2006-05-02 17:36:46 +00:00
Nate Begeman 287dc5be0d Hooray, everyone now uses the same printBasicBlockLabel implementation 
llvm-svn: 28056
 2006-05-02 17:34:51 +00:00
Chris Lattner 67a3aa2aaa Remove dead method 
llvm-svn: 28055
 2006-05-02 17:20:28 +00:00
Chris Lattner 5bc9c583e3 There is no reason to use a virtual method to store this word. 
llvm-svn: 28053
 2006-05-02 17:16:20 +00:00
Chris Lattner bb1c345ec6 Remove the debug machine code emitter. The "FilePrinterEmitter" is more 
useful for debugging.

llvm-svn: 28051
 2006-05-02 16:59:24 +00:00
Nate Begeman b9d4f8324d Extend printBasicBlockLabel a bit so that it can be used to print all 
basic block labels, consolidating the code to do so in one place for each
target.

llvm-svn: 28050
 2006-05-02 05:37:32 +00:00
Nate Begeman 01364fbba8 Update the PPC compilation callback code to not need weird abi-violating 
prologs and epilogs, keep all the asm in one place, and remove use of
compiler builtin functions.

llvm-svn: 28049
 2006-05-02 04:50:05 +00:00
Chris Lattner 2d3a02725d Add pass ID's for various passes, so they can be AddRequiredID. Patch by 
Domagoj Babic!

llvm-svn: 28048
 2006-05-02 04:24:36 +00:00
Jeff Cohen 470f431f44 De-virtualize SwitchSection. 
llvm-svn: 28047
 2006-05-02 03:58:45 +00:00
Jeff Cohen f34ddb1e0d De-virtualize EmitZeroes. 
llvm-svn: 28046
 2006-05-02 03:46:13 +00:00
Jeff Cohen bfe9ffb449 Finish support for Microsoft ML/MASM. May still be a few rough edges. 
llvm-svn: 28045
 2006-05-02 03:11:50 +00:00
Jeff Cohen 24a62a9bc1 Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work). 
llvm-svn: 28044
 2006-05-02 01:16:28 +00:00
Chris Lattner fd0a5478a1 Fix a latent bug that my spiller patch last week exposed: we were leaving 
instructions in the virtregfolded map that were deleted.  Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map.  The solution is to remove entries
from the map when we delete the instructions.

llvm-svn: 28041
 2006-05-01 22:03:24 +00:00
Chris Lattner ab7dbe0cc9 When promoting a load to a reg-reg copy, where the load was a previous 
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.

llvm-svn: 28040
 2006-05-01 21:17:10 +00:00
Chris Lattner 4dee67c2cd Remove previous patch, which wasn't quite right. 
llvm-svn: 28039
 2006-05-01 21:16:03 +00:00
Chris Lattner 85e9909755 Put PHI/INLINEASM into the correct namespace. 
llvm-svn: 28037
 2006-05-01 17:00:49 +00:00
Evan Cheng 0d084fb9ca Dis-favor stores more 
llvm-svn: 28035
 2006-05-01 09:20:44 +00:00
Evan Cheng 24e795496d Bottom up register-pressure reduction scheduler now pushes store operations 
up the schedule. This helps code that looks like this:

loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...

Without this change, the stores and computations are more likely to
interleave:

loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...

This can increase the number of spills if we are unlucky.

llvm-svn: 28033
 2006-05-01 09:14:40 +00:00
Evan Cheng 10ff7b27ce Didn't mean ScheduleDAGList.cpp to make the last checkin. 
llvm-svn: 28030
 2006-05-01 08:56:34 +00:00
Evan Cheng a656242690 Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions. 
llvm-svn: 28029
 2006-05-01 08:54:57 +00:00
Chris Lattner 563f0417d2 Remove %'s from register names when in intel mode. 
llvm-svn: 28027
 2006-05-01 05:53:50 +00:00
Chris Lattner 25f55ae74a Format #APP lines a bit nicer 
llvm-svn: 28026
 2006-05-01 04:11:03 +00:00
Evan Cheng f71f0f2e0b Local spiller kills a store if the folded restore is turned into a copy. 
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.

llvm-svn: 28024
 2006-04-30 08:41:47 +00:00
Jeff Cohen 71c2e0f262 Mingw32 patches supplied by Anton Korobeynikov. 
llvm-svn: 28023
 2006-04-29 18:41:44 +00:00
Chris Lattner 2b48a94413 Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c 
with some changes I have to the new CFE.

llvm-svn: 28022
 2006-04-28 23:33:20 +00:00
Evan Cheng d369603df9 I can't spell: Register, not Regsiter. 
llvm-svn: 28021
 2006-04-28 23:19:39 +00:00
Evan Cheng b244b80172 Implemented x86 inline asm b, h, w, k modifiers. 
llvm-svn: 28020
 2006-04-28 23:11:40 +00:00
Chris Lattner 655d08fda8 Fix InstCombine/2006-04-28-ShiftShiftLongLong.ll 
llvm-svn: 28019
 2006-04-28 22:21:41 +00:00
Chris Lattner 84b49d51be Fix CodeGen/Generic/2006-04-28-Sign-extend-bool.ll 
llvm-svn: 28017
 2006-04-28 21:56:10 +00:00
Evan Cheng 88decded82 Initial caller side support (for CCC only, not FastCC) of 128-bit vector 
passing by value.

llvm-svn: 28015
 2006-04-28 21:29:37 +00:00
Evan Cheng 68a44dc445 Bare-bone X86 inline asm printer support. 
llvm-svn: 28014
 2006-04-28 21:19:05 +00:00
Evan Cheng c5e8ce8b8c Remove the temporary option: -no-isel-fold-inflight 
llvm-svn: 28012
 2006-04-28 18:54:11 +00:00
Evan Cheng 3cd4362ade Implement four-wide shuffle with 2 shufps if no more than two elements come 
from each vector. e.g.
        shuffle(G1, G2, 7, 1, 5, 2)
==>
        movaps _G2, %xmm0
        shufps $151, _G1, %xmm0
        shufps $216, %xmm0, %xmm0

llvm-svn: 28011
 2006-04-28 07:03:38 +00:00
Chris Lattner 1b7a51520c Fix PR743: emit -help output of a tool to cout, not cerr. 
llvm-svn: 28010
 2006-04-28 05:36:25 +00:00
Evan Cheng d43c5c6046 TargetLowering::LowerArguments should return a VBIT_CONVERT of 
FORMAL_ARGUMENTS SDOperand in the return result vector.

llvm-svn: 28009
 2006-04-28 05:25:15 +00:00
Chris Lattner 79c50d96c9 Mapping of physregs can make it so that the designated and input physregs are 
the same.  In this case, don't emit a noop copy.

llvm-svn: 28008
 2006-04-28 04:43:18 +00:00
Chris Lattner e63d808b6e Fix Transforms/Reassociate/2006-04-27-ReassociateVector.ll 
llvm-svn: 28007
 2006-04-28 04:14:49 +00:00
Evan Cheng f0157cb0bc Use movaps instead of movapd for spill / restore. 
llvm-svn: 28005
 2006-04-28 02:23:35 +00:00
Evan Cheng 51ab4498e7 Added a temporary option -no-isel-fold-inflight to control whether a "inflight" 
node can be folded.

llvm-svn: 28003
 2006-04-28 02:09:19 +00:00