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2 Commits

Author SHA1 Message Date
Igor Breger 0f382ccb68 [GlobalISel][X86] Use correct physical register in mir tests.NFC. 
llvm-svn: 313479
 2017-09-17 08:30:42 +00:00
Igor Breger d5b59cf914 [GlobalISel][X86] Support bitwise operations : G_AND, G_OR, G_XOR 
Summary: Support G_AND, G_OR, G_XOR for i8/i16/i32/i64. Selection done via TableGen'erated code.

Reviewers: zvi, guyblank, aymanmus, m_zuckerman

Reviewed By: aymanmus

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D34605

llvm-svn: 306533
 2017-06-28 11:39:04 +00:00