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4 Commits

Author SHA1 Message Date
Igor Breger f1d388a5c5 [GlobalISel][X86] Legalize i1 G_ADD/G_SUB/G_MUL/G_XOR/G_OR/G_AND instructions. 
llvm-svn: 313483
 2017-09-17 11:34:17 +00:00
Igor Breger 28f290fab8 [GlobalISel][X86] Support add i64 in IA32. 
Summary: support G_UADDE instruction selection.

Reviewers: zvi, guyblank

Reviewed By: guyblank

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D33096

llvm-svn: 303255
 2017-05-17 12:48:08 +00:00
Igor Breger 321cf3c650 [GlobalISel][X86] Support float/double and vector types. 
Summary: [GlobalISel][X86] Add support for f32/f64 and vector types in RegisterBank and InstructionSelector.

Reviewers: delena, zvi

Reviewed By: zvi

Subscribers: dberris, rovka, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D30533

llvm-svn: 296856
 2017-03-03 08:06:46 +00:00
Igor Breger b4442f34cd [X86][GlobalISel] Add general-purpose Register Bank 
Summary:
[X86][GlobalISel] Add general-purpose Register Bank.
Add trivial  handling of G_ADD legalization .
Add Regestry Bank selection for COPY and G_ADD  instructions

Reviewers: rovka, zvi, ab, t.p.northover, qcolombet

Reviewed By: qcolombet

Subscribers: qcolombet, mgorny, dberris, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D29771

llvm-svn: 294723
 2017-02-10 07:05:56 +00:00