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4 Commits

Author SHA1 Message Date
Dan Gohman a8dbaeb1df Add an extra example that shouldn't get an and instruction. 
llvm-svn: 54443
 2008-08-07 02:23:06 +00:00
Dan Gohman 86b06335aa Reapply r54147 with a constraint to only use the 8-bit 
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.

Also, change several 16-bit instructions to use 
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.

llvm-svn: 54223
 2008-07-30 18:09:17 +00:00
Dan Gohman 43105328d3 Revert 54147. 
llvm-svn: 54148
 2008-07-29 01:02:18 +00:00
Dan Gohman 26ec56c75c Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation, 
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.

llvm-svn: 54147
 2008-07-28 22:18:25 +00:00