Commit Graph

14 Commits

Author SHA1 Message Date
Conrad Poelman fc5bf040d8 fix check-clang-tools tests that fail due to Windows CRLF line endings
Running check-clang-tools on Windows produces 5 test failures:

Failed Tests (5):
  Clang Tools :: clang-apply-replacements/ClangRenameClassReplacements.cpp
  Clang Tools :: clang-apply-replacements/basic.cpp
  Clang Tools :: clang-apply-replacements/format.cpp
  Clang Tools :: clang-move/move-used-helper-decls.cpp
  Clang Tools :: clang-tidy/infrastructure/export-diagnostics.cpp

Four of these failures are simply due to fixed character position
offsets differing on Windows versus Linux, since Windows line endings
take up two characters instead of one:

clang-apply-replacements/ClangRenameClassReplacements.cpp runs clang-rename -offset=254
clang-apply-replacements/Inputs/basic/file[12].yaml specify e.g.  FileOffset: 148 and Offset: 298
clang-apply-replacements/Inputs/format/{no,yes}.yaml specify e.g.  FileOffset: 94 and Offset: 94
clang-tidy/infrastructure/export-diagnostics.cpp specifies e.g.  CHECK-YAML-NEXT: FileOffset: 30

(The move-used-helper-decls.cpp failure seems more complex; clang-move
adds a blank line after void HelperFun1() {} when
clang-move/Inputs/helper_decls_test.cpp has LF line endings, but does
not add a blank line when the input files has CRLF line endings. That
difference in behavior seems like it may be an actual bug, but I have
yet to track it down.)

Differential Revision: https://reviews.llvm.org/D97625
2022-02-11 15:23:51 -07:00
Wael Yehia c05990a0cc [PATCH] fix location of test case
from D97507.
2021-03-15 09:34:24 -04:00
Wael Yehia be646e3148 llvm-lto: default Relocation Model should be selected by the TargetMachine.
Right now, the createTargetMachine function in LTOBackend.cpp (used by llvm-lto, and other components) selects the default Relocation Model when none is specified in the module.
Other components (such as opt and llc) that construct a TargetMachine delegate the decision on the default value to the polymorphic TargetMachine's constructor.

This commit aligns llvm-lto with other components.

Reviewed By: daltenty, fhahn

Differential Revision: https://reviews.llvm.org/D97507
2021-03-10 17:31:26 -05:00
Jinsong Ji dab8d6104b [PowerPC][AIX] Move the testcase to proper dir 2020-07-30 14:25:59 +00:00
Chris Bowler d5776f250f [NFC][PPC][AIX] Add test coverage for _Complex return values
Differential Revision: https://reviews.llvm.org/D84069
2020-07-29 10:59:52 -04:00
Krzysztof Parzyszek 9ab2cab220 [Hexagon] Move testcase from c1873631d0 to proper location 2020-01-17 12:34:50 -06:00
Brian Cain c1873631d0 [Hexagon] Refactor HexagonShuffle
The check() in HexagonShuffle has been decomposed into smaller steps.
No functionality change is intended with this commit.
2020-01-17 12:22:07 -06:00
Yi-Hong Lyu 00e85f7535 Move csr-save-restore-order.ll to the right place
llvm-svn: 361306
2019-05-21 20:28:31 +00:00
Yi-Hong Lyu 6e19543a2a [PowerPC][NFC] Add a tests for Reordering CSR reloads in epilogue to follow the same order as CSR saves in the prologue
llvm-svn: 361299
2019-05-21 19:42:57 +00:00
Fangrui Song 041c377a59 [X86] Move files to correct directories after D60552
llvm-svn: 360022
2019-05-06 09:24:36 +00:00
Luo, Yuanke 844f662932 Enable intrinsics of AVX512_BF16, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable intrinsics for VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
For more details about BF16 intrinsic, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference

Patch by LiuTianle

Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, spatel, RKSimon

Reviewed By: craig.topper

Subscribers: mgorny, cfe-commits

Tags: #clang

Differential Revision: https://reviews.llvm.org/D60552

llvm-svn: 360018
2019-05-06 08:25:11 +00:00
Luo, Yuanke beec41c656 Enable AVX512_BF16 instructions, which are supported for BFLOAT16 in Cooper Lake
Summary:
1. Enable infrastructure of AVX512_BF16, which is supported for BFLOAT16 in Cooper Lake;
2. Enable VCVTNE2PS2BF16, VCVTNEPS2BF16 and DPBF16PS  instructions, which are Vector Neural Network Instructions supporting BFLOAT16 inputs and conversion instructions from IEEE single precision.
VCVTNE2PS2BF16: Convert Two Packed Single Data to One Packed BF16 Data.
VCVTNEPS2BF16: Convert Packed Single Data to Packed BF16 Data.
VDPBF16PS: Dot Product of BF16 Pairs Accumulated into Packed Single Precision.
For more details about BF16 isa, please refer to the latest ISE document: https://software.intel.com/en-us/download/intel-architecture-instruction-set-extensions-programming-reference

Author: LiuTianle

Reviewers: craig.topper, smaslov, LuoYuanke, wxiao3, annita.zhang, RKSimon, spatel

Reviewed By: craig.topper

Subscribers: kristina, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D60550

llvm-svn: 360017
2019-05-06 08:22:37 +00:00
Chih-Mao Chen 23e23836d5 Move tests in r357996 to correct location within monorepo
llvm-svn: 357997
2019-04-09 11:46:47 +00:00
Chih-Mao Chen 00100b5d0d [RISCV] Rewrite tests to use llvm-mc/llvm-objdump
Previously the tests in lld for RISC-V were given in yaml format as
LLVM's RISC-V assembler support was incomplete. Now that the
assembler/disassembler has matured we can rewrite all tests to use
LLVM's tools.

Differential Revision: https://reviews.llvm.org/D60415

llvm-svn: 357996
2019-04-09 11:39:50 +00:00