6f6d739b6e
TableGen should not ignore BX instructions for the ARM disassembler. pr9368.
...
llvm-svn: 126931
2011-03-03 07:19:52 +00:00
ec84568904
pr9367: Add missing predicated BLX instructions.
...
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.
llvm-svn: 126915
2011-03-03 01:41:01 +00:00
b8b6041734
Fixes an assertion failure while disassembling ARM rsbs reg/reg form.
...
Patch by Ted Kremenek!
llvm-svn: 126895
2011-03-02 23:08:33 +00:00
58775fea6f
Fix the arm's disassembler for blx that was building an MCInst without the
...
needed two predicate operands before the imm operand.
llvm-svn: 126662
2011-02-28 18:46:31 +00:00
34770edf43
Fixed a bug in the enhanced disassembler that caused
...
it to ignore valid uses of FS and GS as additional
base registers in address computations. Added a test
case for this.
llvm-svn: 126302
2011-02-23 03:31:28 +00:00
c1b7775e0f
Added a testcase for the enhanced disassembly bug
...
fixed in r126147, where a field in the X86 decode
structure was being read as bits, not bytes.
llvm-svn: 126182
2011-02-22 02:19:18 +00:00
9cd43977c3
Add assembly parsing support for "msr" and also fix its encoding. Also add
...
testcases for the disassembler to make sure it still works for "msr".
llvm-svn: 125948
2011-02-18 19:45:59 +00:00
90d1dfe4c6
Fix encoding and add parsing support for the arm/thumb CPS instruction:
...
- Add custom operand matching for imod and iflags.
- Rename SplitMnemonicAndCC to SplitMnemonic since it splits more than CC
from mnemonic.
- While adding ".w" as an operand, don't change "Head" to avoid passing the
wrong mnemonic to ParseOperand.
- Add asm parser tests.
- Add disassembler tests just to make sure it can catch all cps versions.
llvm-svn: 125489
2011-02-14 13:09:44 +00:00
4ebf471c9b
Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.
...
llvm-svn: 125127
2011-02-08 22:39:40 +00:00
775eec2280
PR9030: Fix disassembly of ARM "mov pc, lr" instruction.
...
Patch by Jyun-Yan You.
llvm-svn: 124492
2011-01-28 17:50:30 +00:00
ec47597ecd
As far as I can tell, unified syntax uses c0-c15 instead of cr0-cr15 for mcr and friends.
...
llvm-svn: 123407
2011-01-13 22:38:16 +00:00
9f9a10691a
Correctly disassemble truncated asm.
...
Patch by Richard Simth.
llvm-svn: 122962
2011-01-06 16:48:42 +00:00
ae58e7b179
Teach the MBlaze disassembler to disassemble special purpose registers.
...
llvm-svn: 122269
2010-12-20 21:18:04 +00:00
99ea8a3510
Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.
...
llvm-svn: 121082
2010-12-07 00:45:21 +00:00
ca7eaaafda
When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's the
...
32-bit wide version by adding the .w suffix.
llvm-svn: 120838
2010-12-03 20:33:01 +00:00
943fb60b1f
Add correct encodings for STRD and LDRD, including fixup support. Additionally, update these to unified syntax.
...
llvm-svn: 120589
2010-12-01 19:18:46 +00:00
307e4688c5
Now that the MBlaze backend is in its own directory, split the test cases into multiple files for different types of instructions.
...
llvm-svn: 119580
2010-11-17 22:54:43 +00:00
2cd8b08207
Segregate tests by target.
...
llvm-svn: 119050
2010-11-14 18:14:32 +00:00
82471189b7
Fixed error and re-enabled MBlaze MC disassembler tests.
...
llvm-svn: 118987
2010-11-13 05:48:21 +00:00
bee283837f
This test stops after disassembling 1 instructions on
...
darwin and, judging from the buildbots, Linux.
Removing it for now, but this is not the right fix,
Wesley please look at it.
llvm-svn: 118977
2010-11-13 03:55:04 +00:00
99837837ec
Add test cases that should have been committed with 118969.
...
llvm-svn: 118974
2010-11-13 02:51:00 +00:00
11d21e8e78
chase owen.
...
llvm-svn: 118124
2010-11-02 23:55:24 +00:00
d0502c1777
tweak this to pass.
...
llvm-svn: 118122
2010-11-02 23:50:17 +00:00
daf7a2a7de
temporarily xfail this.
...
llvm-svn: 118120
2010-11-02 23:44:50 +00:00
9f6c622f88
Fixed handling of immediate operand sizes, which
...
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix. Also added
a test case for this.
llvm-svn: 117084
2010-10-22 01:24:11 +00:00
59351844e1
ARM instructions that are both predicated and set the condition codes
...
have been printed with the "S" modifier after the predicate. With ARM's
unified syntax, they are supposed to go in the other order. We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM. Apparently we don't generate these instructions often because no one
noticed until now. Thanks to Bill Wendling for the testcase!
llvm-svn: 116563
2010-10-15 03:23:44 +00:00
7e72ec6626
Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern
...
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.
llvm-svn: 116432
2010-10-13 21:00:04 +00:00
6296bbbb65
Added a testcase for the ENTER instruction.
...
llvm-svn: 115580
2010-10-05 00:21:40 +00:00
de636ca9a8
Fix vmov.f64 disassembly on targets where sizeof(long) != 8.
...
llvm-svn: 114240
2010-09-17 23:48:07 +00:00
196841144d
add a test of an edge case value for the FP immediate (needs all digits of
...
precision)
llvm-svn: 114028
2010-09-15 21:52:13 +00:00
27ab5fbd2b
Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to register
...
moves. Previously, the immediate was printed as the encoded integer value,
which is incorrect.
llvm-svn: 114021
2010-09-15 21:04:54 +00:00
c7cf42d80b
Reapply r113875 with additional cleanups.
...
"The register specified for a dregpair is the corresponding Q register, so to
get the pair, we need to look up the sub-regs based on the qreg. Create a
lookup function since we don't have access to TargetRegisterInfo here to
be able to use getSubReg(ARM::dsub_[01])."
Additionaly, fix the NEON VLD1* and VST1* instruction patterns not to use
the dregpair modifier for the 2xdreg versions. Explicitly specifying the two
registers as operands is more correct and more consistent with the other
instruction patterns. This enables further cleanup of special case code in the
disassembler as a nice side-effect.
llvm-svn: 113903
2010-09-14 23:54:06 +00:00
942b10f511
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid
...
printing "lsl #0". This fixes the remaining parts of pr7792. Make
corresponding changes for encoding/decoding these instructions.
llvm-svn: 111251
2010-08-17 17:23:19 +00:00
4577f37d49
Add a Thumb2 t2RSBrr instruction for disassembly only.
...
This fixes another part of PR7792.
llvm-svn: 111057
2010-08-13 23:24:25 +00:00
15b3c3d0ac
Move the Thumb2 SSAT and USAT optional shift operator out of the
...
instruction opcode. This fixes part of PR7792.
llvm-svn: 111047
2010-08-13 21:48:10 +00:00
8e8f1c133a
Cleaned up the for-disassembly-only entries in the arm instruction table so that
...
the memory barrier variants (other than 'SY' full system domain read and write)
are treated as one instruction with option operand.
llvm-svn: 110951
2010-08-12 20:46:17 +00:00
74491bb52c
The autogened decoder was confusing the ARM STRBT for ARM USAT, because the .td
...
entry for ARM STRBT is actually a super-instruction for A8.6.199 STRBT A1 & A2.
Recover by looking for ARM:USAT encoding pattern before delegating to the auto-
gened decoder.
Added a "usat" test case to arm-tests.txt.
llvm-svn: 110894
2010-08-12 01:40:54 +00:00
d59c73f998
Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm.
...
Added two test cases to arm-tests.txt.
llvm-svn: 110880
2010-08-11 23:35:12 +00:00
add513112a
Move the ARM SSAT and USAT optional shift amount operand out of the
...
instruction opcode. This also fixes part of PR7792.
llvm-svn: 110875
2010-08-11 23:10:46 +00:00
72de307116
Add an ARM RSCrr instruction for disassembly only.
...
Partial fix for PR7792.
llvm-svn: 110361
2010-08-05 18:59:36 +00:00
adb93e56a3
Add an ARM RSBrr instruction for disassembly only.
...
Partial fix for PR7792.
llvm-svn: 110358
2010-08-05 18:23:43 +00:00
97886d59d1
ARM "rrx" shift operands do not have an immediate. PR7790.
...
llvm-svn: 110292
2010-08-05 00:34:42 +00:00
cd5fc7bef1
Add support for disassembling VMVN (immediate) instructions. PR7747.
...
llvm-svn: 109946
2010-07-31 05:57:44 +00:00
55595fb291
my work on adding segment registers to LEA missed the
...
disassembler. Remove some code from the disassembler to
compensate, unbreaking disassembly of lea's.
llvm-svn: 108226
2010-07-13 04:23:55 +00:00
e7e1cf9fbd
Eliminated the classification of control registers into %ecr_
...
and %rcr_, leaving just %cr_ which is what people expect.
Updated the disassembler to support this unified register set.
Added a testcase to verify that the registers continue to be
decoded correctly.
llvm-svn: 103196
2010-05-06 20:59:00 +00:00
dd56c40591
Thumb instructions which have reglist operands at the end and predicate operands
...
before reglist were not properly handled with respect to IT Block. Fix that by
creating a new method ARMBasicMCBuilder::DoPredicateOperands() used by those
instructions for disassembly. Add a test case.
llvm-svn: 101974
2010-04-21 01:01:19 +00:00
d7209d2d56
When doing Thumb disassembly, there's no need to consider t2ADDrSPi12/t2SUBrSPi12,
...
as their generic counterparts t2ADDri12/t2SUBri12 should suffice.
llvm-svn: 101929
2010-04-20 18:45:24 +00:00
7be315c414
For t2LDRT, t2LDRBT, t2LDRHT, t2LDRSBT, and t2LDRSHT, if Rn(Inst{19-16})=='1111',
...
transform the Opcode to the corresponding t2LDR*pci counterpart.
Ref: A8.6.86 LDRT, A8.6.65 LDRBT, A8.6.77 LDRHT, A8.6.81 LDRSBT, A8.6.85 LDRSHT
llvm-svn: 101915
2010-04-20 17:28:50 +00:00
777346e749
According to A8.6.16 B (Encoding T3) and A8.3 Conditional execution -- A8.3.1
...
Pseudocode details of conditional, Condition bits '111x' indicate the
instruction is always executed. That is, '1111' is a leagl condition field
value, which is now mapped to ARMCC::AL.
Also add a test case for condition field '1111'.
llvm-svn: 101817
2010-04-19 21:19:52 +00:00
cbe3e1a3df
ARM disassembler did not react to recent changes to the NEON instruction table.
...
VLD1q*_UPD and VST1q*_UPD have the ${dst:dregpair} operand now.
llvm-svn: 101784
2010-04-19 16:20:34 +00:00
Bob Wilson