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12373 Commits

Author SHA1 Message Date
Bruno Cardoso Lopes f8198e4311 Lowers block address. Currently asserts when relocation model is not PIC. Patch by Akira Hatanaka 
llvm-svn: 127027
 2011-03-04 20:01:52 +00:00
Devang Patel 906df92d5c XFAIL for all. These tests are darwin specific anyway. 
llvm-svn: 127022
 2011-03-04 19:38:10 +00:00
Nick Lewycky 41c529bd09 Revert broken srem logic from r126991. 
llvm-svn: 127021
 2011-03-04 19:26:08 +00:00
Devang Patel a0d73fd65e Disable ARMGlobalMerge on darwin. The debugger is not yet able to extract individual variable's info from merged global. 
llvm-svn: 127019
 2011-03-04 19:11:05 +00:00
Kalle Raiskila a1d947dd14 Allow vector shifts (shl,lshr,ashr) on SPU. 
There was a previous implementation with patterns that would 
have matched e.g. 
	shl <v4i32> <i32>,
but this is not valid LLVM IR so they never were selected.

llvm-svn: 126998
 2011-03-04 13:19:18 +00:00
Kalle Raiskila 3531e9b0d9 Allow load from constant on SPU. 
A 'load <4 x i32>* null' crashes llc before this fix.

llvm-svn: 126995
 2011-03-04 12:00:11 +00:00
Nick Lewycky 8e3a79da9f Fold "icmp pred (srem X, Y), Y" like we do for urem. Handle signed comparisons 
in the urem case, though not the other way around. This is enough to get #3 from
PR9343!

llvm-svn: 126991
 2011-03-04 10:06:52 +00:00
Nick Lewycky 3cec6f5563 Teach instruction simplify to use constant ranges to solve problems of the form 
"icmp pred %X, CI" and a number of examples where "%X = binop %Y, CI2".

Some of these cases (div and rem) used to make it through opt -O2, but the
others are probably now making code elsewhere redundant (probably instcombine).

llvm-svn: 126988
 2011-03-04 07:00:57 +00:00
Eli Friedman 5aa4c68eca Followup to r126970: add 64-bit encoding tests for str with reg operand. 
llvm-svn: 126987
 2011-03-04 04:06:47 +00:00
Eli Friedman f63614a982 PR9377: Handle x86 str with register operand in a way consistent with gas. 
llvm-svn: 126970
 2011-03-04 00:10:17 +00:00
Eli Friedman d8a555bb3b Revert r123908; the code in question is completely untested and wrong. 
llvm-svn: 126964
 2011-03-03 22:33:23 +00:00
Joerg Sonnenberger 852ab890b5 Bug#9033: For the ELF assembler output, always quote the section name. 
llvm-svn: 126963
 2011-03-03 22:31:08 +00:00
Richard Osborne af52c52569 Optimize fprintf -> iprintf if there are no floating point arguments 
and siprintf is available on the target.

llvm-svn: 126940
 2011-03-03 14:20:22 +00:00
Richard Osborne 2dfb888392 Optimize sprintf -> siprintf if there are no floating point arguments 
and siprintf is available on the target.

llvm-svn: 126937
 2011-03-03 14:09:28 +00:00
Richard Osborne 815de536e5 Optimize printf -> iprintf if there are no floating point arguments 
and iprintf is available on the target. Currently iprintf is only
marked as being available on the XCore.

llvm-svn: 126935
 2011-03-03 13:17:51 +00:00
Eli Friedman d92d17bf67 PR9352: Always emit a relocation for weak symbols. Not emitting relocations 
for calls to weak symbols with a definition has the appearance of working
with LLVM-generated code because weak symbol definitions are put in their
own sections.

llvm-svn: 126933
 2011-03-03 07:24:36 +00:00
Bob Wilson 6f6d739b6e TableGen should not ignore BX instructions for the ARM disassembler. pr9368. 
llvm-svn: 126931
 2011-03-03 07:19:52 +00:00
Bill Wendling 34c1ccf1f9 Check the ASM, not LLVM IR. 
llvm-svn: 126918
 2011-03-03 02:02:12 +00:00
Bob Wilson ec84568904 pr9367: Add missing predicated BLX instructions. 
Patch by Jyun-Yan You, with some minor adjustments and a testcase from me.

llvm-svn: 126915
 2011-03-03 01:41:01 +00:00
Bill Wendling 8c68af9092 Testcase for r126913. 
llvm-svn: 126914
 2011-03-03 01:32:56 +00:00
Stuart Hastings 3e7f2366fb Test case for r126864. Radar 9056407. 
llvm-svn: 126900
 2011-03-02 23:41:40 +00:00
Stuart Hastings e5fe543878 Test case for r126672. Radar 9055247. 
llvm-svn: 126896
 2011-03-02 23:24:44 +00:00
Kevin Enderby b8b6041734 Fixes an assertion failure while disassembling ARM rsbs reg/reg form. 
Patch by Ted Kremenek!

llvm-svn: 126895
 2011-03-02 23:08:33 +00:00
David Greene dd567b214b [AVX] Fix mask predicates for 256-bit UNPCKLPS/D and implement 
missing patterns for them.

      Add a SIMD test subdirectory to hold tests for SIMD instruction
      selection correctness and quality.
'

llvm-svn: 126845
 2011-03-02 17:23:43 +00:00
Cameron Zwarich 5dd2aa2615 Eliminate the unused CodeGenPrepare option to split critical edges. 
llvm-svn: 126825
 2011-03-02 03:31:46 +00:00
Che-Liang Chiou 65b1476031 Extend initial support for primitive types in PTX backend 
- Allow i16, i32, i64, float, and double types, using the native .u16,
  .u32, .u64, .f32, and .f64 PTX types.
- Allow loading/storing of all primitive types.
- Allow primitive types to be passed as parameters.
- Allow selection of PTX Version and Shader Model as sub-target attributes.
- Merge integer/floating-point test cases for load/store.
- Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler.

Patch by Justin Holewinski

llvm-svn: 126824
 2011-03-02 03:20:28 +00:00
Dan Gohman 7290868a1b Don't re-use existing addrec expansions if they contain casts. 
This fixes PR9259.

llvm-svn: 126812
 2011-03-02 01:34:10 +00:00
Evan Cheng 15fed7af3c Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648. 
llvm-svn: 126811
 2011-03-02 01:08:17 +00:00
Anders Carlsson da80afef99 Make InstCombiner::FoldAndOfICmps create a ConstantRange that's the 
intersection of the LHS and RHS ConstantRanges and return "false" when
the range is empty.

This simplifies some code and catches some extra cases.

llvm-svn: 126744
 2011-03-01 15:05:01 +00:00
Nick Lewycky c9d20067cd Optimize "icmp pred (urem X, Y), Y" --> true/false depending on pred. There's 
more work to do here, "icmp ult (urem X, 10), 11" doesn't optimize away yet.
Fixes example 3 from PR9343!

llvm-svn: 126741
 2011-03-01 08:15:50 +00:00
Bill Wendling 3b1459b810 Narrow right shifts need to encode their immediates differently from a normal 
shift.

   16-bit: imm6<5:3> = '001', 8 - <imm> is encded in imm6<2:0>
   32-bit: imm6<5:4> = '01',16 - <imm> is encded in imm6<3:0>
   64-bit: imm6<5> = '1', 32 - <imm> is encded in imm6<4:0>

llvm-svn: 126723
 2011-03-01 01:00:59 +00:00
Eli Friedman 683bbc16c4 Add an obvious missing safety check to DAE::RemoveDeadArgumentsFromCallers. 
llvm-svn: 126720
 2011-03-01 00:33:47 +00:00
Dan Gohman 6564ca0c23 Delete obsolete test. 
llvm-svn: 126680
 2011-02-28 19:58:14 +00:00
Jakob Stoklund Olesen 87d7408f29 Fix typo introduced by r126661: "Fix a typo which ..." 
llvm-svn: 126666
 2011-02-28 19:18:59 +00:00
Kevin Enderby 58775fea6f Fix the arm's disassembler for blx that was building an MCInst without the 
needed two predicate operands before the imm operand.

llvm-svn: 126662
 2011-02-28 18:46:31 +00:00
Evan Cheng 6e3d443646 Fix a typo which cause dag combine crash. rdar://9059537. 
llvm-svn: 126661
 2011-02-28 18:45:27 +00:00
Duncan Sands f66e4611f9 Windows codegen also dies on this, so restrict to the platform it was 
actually tested on.

llvm-svn: 126652
 2011-02-28 14:22:08 +00:00
Duncan Sands feb9926a59 Make this test x86 specific because the ARM backend can't handle it. 
llvm-svn: 126650
 2011-02-28 12:30:47 +00:00
Frits van Bommel 8ae07996c9 Teach SimplifyCFG that (switch (select cond, X, Y)) is better expressed as a branch. 
Based on a patch by Alistair Lynn.

llvm-svn: 126647
 2011-02-28 09:44:07 +00:00
Nick Lewycky 66f4f22f7b srem doesn't actually have the same resulting sign as its numerator, you could 
also have a zero when numerator = denominator. Reverts parts of r126635 and
r126637.

llvm-svn: 126644
 2011-02-28 09:17:39 +00:00
Nick Lewycky 174a705497 Teach InstCombine to fold "(shr exact X, Y) == 0" --> X == 0, fixing #1 from 
PR9343.

llvm-svn: 126643
 2011-02-28 08:31:40 +00:00
Che-Liang Chiou 75a800d3bf Add preliminary support for .f32 in the PTX backend. 
- Add appropriate TableGen patterns for fadd, fsub, fmul.
- Add .f32 as the PTX type for the LLVM float type.
- Allow parameters, return values, and global variable declarations
  to accept the float type.
- Add appropriate test cases.

Patch by Justin Holewinski

llvm-svn: 126636
 2011-02-28 06:34:09 +00:00
Nick Lewycky 6b445419b0 The sign of an srem instruction is the sign of its dividend (the first 
argument), regardless of the divisor. Teach instcombine about this and fix
test7 in PR9343!

llvm-svn: 126635
 2011-02-28 06:20:05 +00:00
Duncan Sands f571290d1e Legalize support for fpextend of vector. PR9309. 
llvm-svn: 126574
 2011-02-27 14:41:27 +00:00
NAKAMURA Takumi d4e5003a3f Target/X86: Always emit "push/pop GPRs" in prologue/epilogue and emit "spill/reload frames" for XMMs. 
It improves Win64's prologue/epilogue but it would not affect ia32 and amd64 (lack of nonvolatile XMMs).

llvm-svn: 126568
 2011-02-27 08:47:19 +00:00
Cameron Zwarich 68f677a612 Fix PR9324 / <rdar://problem/9052489> by handling the case where a PHI has no uses. 
llvm-svn: 126567
 2011-02-27 08:06:01 +00:00
Cameron Zwarich baeb5f1431 Give a test file a more sensible name so that it can hold more test cases. 
llvm-svn: 126566
 2011-02-27 08:05:57 +00:00
Benjamin Kramer 26691d9660 Add some DAGCombines for (adde 0, 0, glue), which are useful to optimize legalized code for large integer arithmetic. 
1. Inform users of ADDEs with two 0 operands that it never sets carry
2. Fold other ADDs or ADDCs into the ADDE if possible

It would be neat if we could do the same thing for SETCC+ADD eventually, but we can't do that in target independent code.

llvm-svn: 126557
 2011-02-26 22:48:07 +00:00
Chris Lattner 78178749e9 split this test into arch specific pieces, so the ARM 
test isn't run when the arm backend isn't built.  This
fixes PR9327

llvm-svn: 126500
 2011-02-25 19:06:35 +00:00
Benjamin Kramer ceb5daa567 Revert "SimplifyCFG: GEPs with just one non-constant index are also cheap." 
Yes, there are other types than i8* and GEPs on them can produce an add+multiply.
We don't consider that cheap enough to be speculatively executed.

llvm-svn: 126481
 2011-02-25 10:33:33 +00:00