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34 Commits

Author SHA1 Message Date
Zlatko Buljan cba9f80ba8 [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 
Differential Revision: http://reviews.llvm.org/D18824

llvm-svn: 275050
 2016-07-11 07:41:56 +00:00
Zlatko Buljan d2ed9c6c2c [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and NOR instructions 
Differential Revision: http://reviews.llvm.org/D16719

llvm-svn: 272764
 2016-06-15 07:46:24 +00:00
Hrvoje Varga c962c4936e [mips][microMIPS] Implement BOVC, BNVC, EXT, INS and JALRC instructions 
Differential Revision: http://reviews.llvm.org/D11798

llvm-svn: 272259
 2016-06-09 12:57:23 +00:00
Zlatko Buljan e663e34e79 [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructions 
Differential Revision: http://reviews.llvm.org/D18352

llvm-svn: 270030
 2016-05-19 07:31:28 +00:00
Zlatko Buljan 6afea51a58 [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add CodeGen support 
Differential Revision: http://reviews.llvm.org/D15418

llvm-svn: 269883
 2016-05-18 06:54:59 +00:00
Zoran Jovanovic 84e4d59e47 [mips][microMIPS] Implement BEQZC and BNEZC instructions 
Differential Revision: http://reviews.llvm.org/D15417

llvm-svn: 269755
 2016-05-17 11:10:15 +00:00
Hrvoje Varga cf6a78192b Revert "[mips][microMIPS] Implement CFC*, CTC* and LDC* instructions" 
This reverts commit r269176 as it caused test-suite failure.

llvm-svn: 269287
 2016-05-12 12:46:06 +00:00
Hrvoje Varga 52c9bed858 [mips][microMIPS] Implement CFC*, CTC* and LDC* instructions 
Differential Revision: http://reviews.llvm.org/D19713

llvm-svn: 269176
 2016-05-11 12:12:24 +00:00
Zlatko Buljan ba553a6e0a [mips][microMIPS] Implement LWP and SWP instructions 
Differential Revision: http://reviews.llvm.org/D10640

llvm-svn: 268896
 2016-05-09 08:07:28 +00:00
Zlatko Buljan 4807f829b4 [mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions 
Differential Revision: http://reviews.llvm.org/D19857

llvm-svn: 268491
 2016-05-04 12:02:12 +00:00
Zlatko Buljan 29813620bc [mips][microMIPS] Add CodeGen support for SLL16, SRL16, SLL, SLLV, SRA, SRAV, SRL and SRLV instructions 
Differential Revision: http://reviews.llvm.org/D17989

llvm-svn: 267693
 2016-04-27 11:02:23 +00:00
Hrvoje Varga c2dd5d223a [mips][microMIPS] Revert commit r267137 
Commit r267137 was the reason for failing tests in LLVM test suite.

llvm-svn: 267419
 2016-04-25 15:40:08 +00:00
Zlatko Buljan b43d4bcbd5 [mips][microMIPS] Revert commit r266977 
Commit r266977 was reason for failing LLVM test suite with error message: fatal error: error in backend: Cannot select: t17: i32 = rotr t2, t11 ...

llvm-svn: 267418
 2016-04-25 15:34:57 +00:00
Zoran Jovanovic f6344ff295 [mips][microMIPS] Revert commit r266861. 
Commit r266861 was the reason for failing tests in LLVM test suite.

llvm-svn: 267166
 2016-04-22 16:53:15 +00:00
Hrvoje Varga 5560998250 [mips][microMIPS] Implement SLT, SLTI, SLTIU, SLTU microMIPS32r6 instructions 
Differential Revision: http://reviews.llvm.org/D19354

llvm-svn: 267137
 2016-04-22 11:18:40 +00:00
Zlatko Buljan ae720dbbb6 [mips][microMIPS] Implement DVP, EVP and JALRC.HB instructions 
Differential Revision: http://reviews.llvm.org/D18687

llvm-svn: 267114
 2016-04-22 06:44:34 +00:00
Zlatko Buljan dd4151504a [mips][microMIPS] Implement TLBP, TLBR, TLBWI and TLBWR instructions 
Differential Revision: http://reviews.llvm.org/D18855

llvm-svn: 266980
 2016-04-21 11:32:40 +00:00
Zlatko Buljan d370f440e2 [mips][microMIPS] Implement LL, SC, MOVEP, ROTR, ROTRV and SYSCALL instructions and add tests for LWM32 and SWM32 
Differential Revision: http://reviews.llvm.org/D19150

llvm-svn: 266977
 2016-04-21 11:01:51 +00:00
Zoran Jovanovic fdbd0a37c1 [mips][microMIPS] Implement BGEC, BGEUC, BLTC, BLTUC, BEQC and BNEC instructions 
Differential Revision: http://reviews.llvm.org/D14206

llvm-svn: 266873
 2016-04-20 14:07:46 +00:00
Hrvoje Varga 117625aaf3 [mips][microMIPS]Implement CFC*, CTC* and LDC* instructions 
Differential Revision: http://reviews.llvm.org/D18640

llvm-svn: 266861
 2016-04-20 06:34:48 +00:00
Zlatko Buljan 6221be8e46 [mips][microMIPS] Implement MFC*, MFHC* and DMFC* instructions 
Differential Revision: http://reviews.llvm.org/D17334

llvm-svn: 265002
 2016-03-31 08:51:24 +00:00
Hrvoje Varga 2cb74ac3c3 [mips][microMIPS] Implement MTC*, MTHC* and DMTC* instructions 
Differential Revision: http://reviews.llvm.org/D17328

llvm-svn: 264246
 2016-03-24 08:02:09 +00:00
Zlatko Buljan f034021443 [mips][microMIPS] Implement TLBINV and TLBINVF instructions 
Differential Revision: http://reviews.llvm.org/D16849

llvm-svn: 261211
 2016-02-18 14:10:52 +00:00
Zlatko Buljan 5da2f6cd03 [mips][microMIPS] Implement DERET and DI instructions and check size operand for EXT and DEXT* instructions 
Differential Revision: http://reviews.llvm.org/D15570

llvm-svn: 256152
 2015-12-21 13:08:58 +00:00
Zlatko Buljan 48f1f39bfe Revert r254897 "[mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions" 
Commited patch was intended to implement LH, LHE, LHU and LHUE instructions.
After commit test-suite failed with error message in the form of:
fatal error: error in backend: Cannot select: t124: i32,ch = load<LD2[%d](tbaa=<0x94acc48>), sext from i16> t0, t2, undef:i32
For that reason I decided to revert commit r254897 and make new patch which besides implementation and standard regression tests will also have dedicated tests (CodeGen) for the above error. 

llvm-svn: 255109
 2015-12-09 13:07:45 +00:00
Zlatko Buljan 1a01c15027 [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions 
Differential Revision: http://reviews.llvm.org/D9824

llvm-svn: 254897
 2015-12-07 08:29:31 +00:00
Hrvoje Varga e51b0e13f3 [mips][microMIPS] Implement RECIP.fmt, RINT.fmt, ROUND.L.fmt, ROUND.W.fmt, SEL.fmt, SELEQZ.fmt, SELNEQZ.fmt and CLASS.fmt 
Differential Revision: http://reviews.llvm.org/D13885

llvm-svn: 254405
 2015-12-01 11:59:21 +00:00
Zoran Jovanovic a887b36167 [mips][microMIPS] Fix issue with offset operand of BALC and BC instructions 
Value of offset operand for microMIPS BALC and BC instructions is currently shifted 2 bits, but it should be 1 bit.
Differential Revision: http://reviews.llvm.org/D14770

llvm-svn: 254296
 2015-11-30 12:56:18 +00:00
Zlatko Buljan 797c2aec6b [mips][microMIPS] Implement LWM16, SB16, SH16, SW16, SWSP and SWM16 instructions 
Differential Revision: http://reviews.llvm.org/D11406

llvm-svn: 252885
 2015-11-12 13:21:33 +00:00
Daniel Sanders ea4f653d18 [mips][ias] Range check uimm2 operands and fix a bug this revealed. 
Summary:
The bug was that the MIPS32R6/MIPS64R6/microMIPS32R6 versions of LSA and DLSA
(unlike the MSA version) failed to account for the off-by-one encoding of the
immediate. The range is actually 1..4 rather than 0..3.

Reviewers: vkalintiris

Subscribers: atanasyan, dsanders, llvm-commits

Differential Revision: http://reviews.llvm.org/D14015

llvm-svn: 252295
 2015-11-06 12:22:31 +00:00
Hrvoje Varga 18148671ee [mips][microMIPS] Implement PAUSE, RDHWR, RDPGPR, SDBBP, SSNOP, SYNC, SYNCI and WAIT instructions 
Differential Revision: http://reviews.llvm.org/D12628

llvm-svn: 251510
 2015-10-28 11:04:29 +00:00
Hrvoje Varga 3c88fbd367 [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructions 
Differential Revision: http://reviews.llvm.org/D11633

llvm-svn: 250511
 2015-10-16 12:24:58 +00:00
Hrvoje Varga 3a3c4b8a39 [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 instructions 
Differential Revision: http://reviews.llvm.org/D11292#inline-103143

llvm-svn: 250381
 2015-10-15 08:39:07 +00:00
Daniel Sanders d245267be0 [mips][disassembler] Merged disassembler tests into the corresponding ISA/ASE subdirectories. 
llvm-svn: 249384
 2015-10-06 10:02:35 +00:00