llvm-project

Author	SHA1	Message	Date
Akira Hatanaka	5624707684	Fix test cases. Generate code for Mips32r1 unless a Mips32r2 feature is tested. llvm-svn: 139433	2011-09-09 23:14:58 +00:00
Akira Hatanaka	4444daeec5	Drop support for Mips1 and Mips2. llvm-svn: 139405	2011-09-09 20:45:50 +00:00
Akira Hatanaka	df1df7edf1	Change default target architecture from Mips1 to Mips32r1 in preparation for removing support for Mips1 and Mips2. This change and the ones that follow have been discussed with and approved by Bruno. llvm-svn: 139344	2011-09-09 01:13:27 +00:00
Akira Hatanaka	2263c10946	Fix handling of double precision loads and stores when Mips1 is targeted. Mips1 does not support double precision loads or stores, therefore two single precision loads or stores must be used in place of these instructions. This patch treats double precision loads and stores as if they are legal instructions until MCInstLowering, instead of generating the single precision instructions during instruction selection or Prolog/Epilog code insertion. Without the changes made in this patch, llc produces code that has the same problem described in r137484 or bails out when MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before register allocation. llvm-svn: 137711	2011-08-16 03:51:51 +00:00
Akira Hatanaka	a535270d91	Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons. llvm-svn: 128650	2011-03-31 18:26:17 +00:00