Commit Graph

95714 Commits

Author SHA1 Message Date
Quentin Colombet d3126d5fb4 [AArch64][MachineLegalizer] Mark v2s32 G_LOAD as legal.
Actually every 64-bit loads are legal, but right now the API does not
offer a simple way to express that.

llvm-svn: 283829
2016-10-11 00:21:08 +00:00
Rui Ueyama 8af4988f35 Revert r283824 and r283823: Define DbiStreamBuilder::addDbgStream to add stream.
This reverts commit r283824 and r283823 to fix buildbots.

llvm-svn: 283828
2016-10-11 00:15:50 +00:00
Rui Ueyama 914eef6a64 Fix a bug in DbiStreamBuilder::addDbgStream.
This feature will be tested in LLD unit tests.

llvm-svn: 283824
2016-10-10 23:44:04 +00:00
Rui Ueyama 70edd9e41d Define DbiStreamBuilder::addDbgStream to add stream.
Previously, there is no way to create a stream other than pre-defined
special stream such as DBI or IPI. This patch adds a new method,
addDbgStream, to add a debug stream to a PDB file.

Differential Revision: https://reviews.llvm.org/D25356

llvm-svn: 283823
2016-10-10 23:35:36 +00:00
Peter Collingbourne 0da86301ad Revert r283690, "MC: Remove unused entities."
llvm-svn: 283814
2016-10-10 22:49:37 +00:00
Tim Northover bdf1624367 GlobalISel: select G_GLOBAL_VALUE uses on AArch64.
llvm-svn: 283809
2016-10-10 21:50:00 +00:00
Tim Northover ad0acca544 GlobalISel: allow G_GLOBAL_VALUEs in AArch64 legalization.
llvm-svn: 283808
2016-10-10 21:49:53 +00:00
Tim Northover 2fda4b08ae GlobalISel: support selecting G_GEP instructions.
They're basically just an alias for G_ADD on AArch64.

llvm-svn: 283807
2016-10-10 21:49:49 +00:00
Tim Northover 4edc60d785 GlobalISel: support selecting constants on AArch64.
llvm-svn: 283806
2016-10-10 21:49:42 +00:00
Dehao Chen 84287abf43 Rename isHotFunction/isColdFunction to isFunctionEntryHot/isFunctionEntryCold. (NFC)
This is in preparation for https://reviews.llvm.org/D25048

llvm-svn: 283805
2016-10-10 21:47:28 +00:00
Hal Finkel fcd2421667 [SelectionDAGBuilder] Support llvm.flt.rounds on targets where i32 is not legal
Add integer expansion for FLT_ROUNDS_ for targets where i32 is not a legal
type.

Patch by Edward Jones, thanks!

Differential Revision: https://reviews.llvm.org/D24459

llvm-svn: 283797
2016-10-10 20:45:15 +00:00
Adrian Prantl 3bfe1093df Teach llvm::StripDebugInfo() about global variable !dbg attachments.
This is a regression introduced by the global variable ownership
reversal performed in r281284.

rdar://problem/28448075

llvm-svn: 283784
2016-10-10 17:53:33 +00:00
Justin Lebar 611c5c225a Use unique_ptr in LLVMContextImpl's constant maps.
Reviewers: timshen

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D25419

llvm-svn: 283767
2016-10-10 16:26:13 +00:00
Alexandros Lamprineas 20e9ddba73 [ARM] Fix invalid VLDM/VSTM access when targeting Big Endian with NEON
The instructions VLDM/VSTM can only access word-aligned memory
locations and produce alignment fault if the condition is not met.

The compiler currently generates VLDM/VSTM for v2f64 load/store
regardless the alignment of the memory access. Instead, if a v2f64
load/store is not word-aligned, the compiler should generate
VLD1/VST1. For each non double-word-aligned VLD1/VST1, a VREV
instruction should be generated when targeting Big Endian.

Differential Revision: https://reviews.llvm.org/D25281

llvm-svn: 283763
2016-10-10 16:01:54 +00:00
Nirav Dave f43cc9f8b5 Add return type for checkForValidSection parsing function. NFC Intended.
llvm-svn: 283761
2016-10-10 15:24:54 +00:00
Zvi Rackover 2a21f125bd [X86] Prefer rotate by 1 over rotate by imm
Summary:
Rotate by 1 is translated to 1 micro-op, while rotate with imm8 is translated to 2 micro-ops.

Fixes pr30644.

Reviewers: delena, igorb, craig.topper, spatel, RKSimon

Differential Revision: https://reviews.llvm.org/D25399

llvm-svn: 283758
2016-10-10 14:43:55 +00:00
Chris Dewhurst 850131213f This pass, fixing an erratum in some LEON 2 processors ensures that the SDIV instruction is not issued, but replaced by SDIVcc instead, which does not exhibit the error. Unit test included.
Differential Review: https://reviews.llvm.org/D24660

llvm-svn: 283727
2016-10-10 08:53:06 +00:00
Daniel Jasper 0dea246b4f Fix WebAssembly build after r283702.
llvm-svn: 283723
2016-10-10 06:49:55 +00:00
Craig Topper 9ece2f7529 [AVX-512] Add missing pattern sext or zext from bytes to quad words with a 128-bit load as input.
llvm-svn: 283720
2016-10-10 06:25:48 +00:00
Michael Zuckerman 3eeac2d56b [x86][inline-asm][llvm] accept 'v' constraint
Commit in the name of:Coby Tayree
1.'v' constraint for (x86) non-avx arch imitates the already implemented 'x' constraint, i.e. allows XMM{0-15} & YMM{0-15} depending on the apparent arch & mode (32/64).
2.for the avx512 arch it allows [X,Y,Z]MM{0-31} (mode dependent)

This patch applies the needed changes to clang
 clang patch: https://reviews.llvm.org/D25004

Differential Revision: D25005
 

llvm-svn: 283717
2016-10-10 05:48:56 +00:00
Dylan McKay 1a523767dc [AVR] Enable generation of the TableGen assembly writer tables
This also changes the order of the statements in CMakeLists.txt to be
alphabetical.

llvm-svn: 283711
2016-10-10 01:28:45 +00:00
Craig Topper 64378f4378 [AVX-512] Port 128 and 256-bit memory->register sign/zero extend patterns from SSE file. Also add a minimal set for 512-bit.
llvm-svn: 283704
2016-10-09 23:08:39 +00:00
Craig Topper 29558b8284 [X86] Remove redundant patterns. The same pattern appears a few lines up.
llvm-svn: 283703
2016-10-09 23:08:33 +00:00
Mehdi Amini f42454b94b Move the global variables representing each Target behind accessor function
This avoids "static initialization order fiasco"

Differential Revision: https://reviews.llvm.org/D25412

llvm-svn: 283702
2016-10-09 23:00:34 +00:00
Elena Demikhovsky 5b10aa1f1e DAG: Setting Masked-Expand-Load as a variant of Masked-Load node
Masked-expand-load node represents load operation that loads a variable amount of elements from memory according to amount of "true" bits in the mask and expands the loaded elements according to their position in the mask vector.
Right now, the node is used in intrinsics for VEXPAND* instructions. 
The work is done towards implementation of masked.expandload and masked.compressstore intrinsics.

Differential Revision: https://reviews.llvm.org/D25322

llvm-svn: 283694
2016-10-09 10:48:52 +00:00
Craig Topper 43973154dd [AVX-512] Fix execution domain for EVEX encoded VINSERTPS.
llvm-svn: 283692
2016-10-09 06:41:47 +00:00
Peter Collingbourne cc723cccab MC: Remove unused entities.
llvm-svn: 283691
2016-10-09 04:39:13 +00:00
Peter Collingbourne 5c924d7117 Target: Remove unused entities.
llvm-svn: 283690
2016-10-09 04:38:57 +00:00
Craig Topper e30cb00dc0 [AVX-512] Add subvector insert and extract to load/store folding tables.
llvm-svn: 283689
2016-10-09 03:54:13 +00:00
Craig Topper 4262d53024 [AVX-512] Add the vector down convert instructions to the store folding tables.
llvm-svn: 283687
2016-10-09 03:54:05 +00:00
Kostya Serebryany 7abb95d3b3 [libFuzzer] make a test less flaky
llvm-svn: 283686
2016-10-09 03:45:38 +00:00
Kostya Serebryany c5325ed29d [libFuzzer] when shrinking the corpus, delete evicted files previously created by the current process
llvm-svn: 283682
2016-10-08 23:24:45 +00:00
Kostya Serebryany 9adc7c8b4a [libFuzzer] control the reload interval by a flag, make it 10 seconds by default
llvm-svn: 283676
2016-10-08 22:12:14 +00:00
Kostya Serebryany cd04ec25dd [libFuzzer] fix use-after-free in libFuzzer found by ... fuzzing.
llvm-svn: 283675
2016-10-08 21:57:48 +00:00
Mehdi Amini 732afdd09a Turn cl::values() (for enum) from a vararg function to using C++ variadic template
The core of the change is supposed to be NFC, however it also fixes
what I believe was an undefined behavior when calling:

 va_start(ValueArgs, Desc);

with Desc being a StringRef.

Differential Revision: https://reviews.llvm.org/D25342

llvm-svn: 283671
2016-10-08 19:41:06 +00:00
Craig Topper 086f0c1401 [AVX-512] Fix a bug in getLargestLegalSuperClass where we inflated to VR128X/VR256X even when VLX isn't supported.
This seems to have been responsible for the XMM16-31 spills observed in PR29112. With this fixed the test case has been modified to no longer have a spill of XMM16.

llvm-svn: 283668
2016-10-08 18:49:57 +00:00
Colin LeMahieu c69f7ff6c0 [Hexagon] Adding change of flow max 1 (cofMax1) TS flag for marking this restriction rather than implying it from TypeJR.
llvm-svn: 283665
2016-10-08 17:18:51 +00:00
Teresa Johnson 897bab9b35 [ThinLTO] Record calls to aliases
Summary:
When there is a call to an alias in the same module, we were not
adding a call edge. So we could incorrectly think that the alias
was dead if it was inlined in that function, despite having a
reference imported elsewhere. This resulted in unsats at link time.

Add a call edge when the call is to an alias.

Reviewers: davide, mehdi_amini

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D25384

llvm-svn: 283664
2016-10-08 16:11:42 +00:00
Sebastian Pop eb65d72d9c [AArch64] Avoid generating indexed vector instructions for Exynos
Avoid generating indexed vector instructions for Exynos. This is needed for
fmla/fmls/fmul/fmulx. For example, the instruction

  fmla v0.4s, v1.4s, v2.s[1]

is less efficient than the instructions

  dup v2.4s, v2.s[1]
  fmla v0.4s, v1.4s, v2.4s

Patch written by Abderrazek Zaafrani.

Differential Revision: https://reviews.llvm.org/D21571

llvm-svn: 283663
2016-10-08 12:30:07 +00:00
Adam Nemet ee5cf031ce [OptRemarks] Remove non-printable chars from function name
Value names may be prefixed with a binary '1' to indicate that the
backend should not modify the symbols due to any platform naming
convention.

This should not show up in the YAML opt record file because it breaks
the YAML parser.

llvm-svn: 283656
2016-10-08 04:47:20 +00:00
Mehdi Amini f82bda0a7a ThinLTO: don't perform incremental LTO on module without a hash
Clang always emit a hash for ThinLTO, but as other frontend are
starting to use ThinLTO, this could be a serious bug.

Differential Revision: https://reviews.llvm.org/D25379

llvm-svn: 283655
2016-10-08 04:44:23 +00:00
Mehdi Amini 00fa1409ec ThinLTO: handles modules with empty summaries
We need to add an entry in the combined-index for modules that have
a hash but otherwise empty summary, this is needed so that we can
get the hash for the module.

Also, if no entry is present in the combined index for a module, we
need to skip it when trying to compute a cache entry.

Differential Revision: https://reviews.llvm.org/D25300

llvm-svn: 283654
2016-10-08 04:44:18 +00:00
Kyle Butt 2facd194a2 Revert "Codegen: Tail-duplicate during placement."
This reverts commit 71c312652c10f1855b28d06697c08d47e7a243e4.

llvm-svn: 283647
2016-10-08 01:47:05 +00:00
Dylan McKay f96ffe1ebf [AVR] Add backend dependencies to MCTargetDesc/LLVMBuild.txt
llvm-svn: 283642
2016-10-08 01:14:23 +00:00
Zachary Turner 3b14764ce5 [pdb] Dump Module Symbols to Yaml.
This is the first step towards round-tripping symbol information,
and thusly being able to write symbol information to a PDB.

This patch writes the symbol information for each compiland to
the Yaml when running in pdb2yaml mode.  There's still some loose
ends, such as what to do about relocations (necessary in order to
print linkage names), how to print enums with friendly names, and
how to give the dumper access to the StringTable, but this is a
good first start.

llvm-svn: 283641
2016-10-08 01:12:01 +00:00
Dylan McKay 552b7856d3 Fix incorrect assertion in AVRFrameLowering.cpp
This wasn't looking at the right instruction, and would always fail.

llvm-svn: 283640
2016-10-08 01:10:36 +00:00
Dylan McKay b16b6d5739 [AVR] Don't worry about call frame size when initializing frame pointer
We previously only used the frame pointer if the frame pointer was too
big. This was to work around a bug (described in this old commit)

https://sourceforge.net/p/avr-llvm/code/204/tree//llvm/trunk/AVR/AVRFrameLowering.cpp?diff=50d64d912718465cb887d17a:203

I mistakenly invered the condition assuming it was a typo. I am now
removing it because it doesn't seem to be a problem anymore (plus it's a
dirty hack).

llvm-svn: 283639
2016-10-08 01:10:31 +00:00
Dylan McKay 7c2d41aa9f [AVR] Don't shadow container while iterating in range-based loop
This works on clang, but fails on GCC 4.6

llvm-svn: 283638
2016-10-08 01:09:06 +00:00
Dylan McKay a1a944e3cb [AVR] Use references rather than pointers in AVRISelLowering
llvm-svn: 283636
2016-10-08 01:06:21 +00:00
Dylan McKay 12109e7314 Allow a maximum of 64 bits to be returned in registers
The rest spills to the stack

Authored by Jake Goulding

llvm-svn: 283635
2016-10-08 01:05:09 +00:00