Commit Graph

40332 Commits

Author SHA1 Message Date
Pablo Barrio f9e0d0b7d0 [JumpThreading] Unfold selects that depend on the same condition
Summary:
These are good candidates for jump threading. This enables later opts
(such as InstCombine) to combine instructions from the selects with
instructions out of the selects. SimplifyCFG will fold the select
again if unfolding wasn't worth it.

Patch by James Molloy and Pablo Barrio.

Reviewers: reames, bkramer, mcrosier, gberry, haicheng, jmolloy, sebpop

Subscribers: jojo, rengolin, llvm-commits

Differential Revision: https://reviews.llvm.org/D25477

llvm-svn: 284971
2016-10-24 13:04:45 +00:00
Simon Dardis 9c34854833 [mips] synci microMIPS instruction definition.
Add synci to the microMIPS instruction definitions, mark the MIPS sync & synci
as not being part of microMIPS. This does not cover the sync instruction alias,
as that will be handled with a different patch. Add sync to the valid tests for
microMIPS.

Reviewers: vkalintiris

Differential Revision: https://reviews.llvm.org/D25795

llvm-svn: 284962
2016-10-24 10:23:59 +00:00
Hal Finkel fd448408e3 [llvm-opt-report] Fix unroll-count reporting
Fix the implementation of OptReportLocationInfo's operator < so that contexts
with different unroll counts are reported separately.

llvm-svn: 284957
2016-10-24 05:07:18 +00:00
Craig Topper 8ec5c7326d [AVX-512] Remove masked pmin/pmax intrinsics and autoupgrade to native IR.
Clang patch to replace 512-bit vector and 64-bit element versions with native IR will follow.

llvm-svn: 284955
2016-10-24 04:04:16 +00:00
Sanjay Patel 9ca028c2d6 [DAG] enhance computeKnownBits to handle SRL/SRA with vector splat constant
llvm-svn: 284953
2016-10-23 23:13:31 +00:00
Simon Pilgrim d09c04d267 [CostModel][X86] Added tests for current integer signed/unsigned remainder costs
llvm-svn: 284940
2016-10-23 18:35:02 +00:00
Simon Pilgrim 6ac1e98b09 [X86][SSE] Add SSE41/AVX1 costs for vector shifts.
We were defaulting to SSE2 costs which weren't taking into account the availability of PBLENDW/PBLENDVB to improve merging of per-element shift results.

llvm-svn: 284939
2016-10-23 16:49:04 +00:00
Simon Pilgrim e16b1e2271 [CostModel][X86] Added tests for current integer trunc costs
llvm-svn: 284938
2016-10-23 15:17:52 +00:00
Simon Pilgrim d3829c89bc [X86][AVX512VL] Added support for combining target 256-bit shuffles to AVX512VL VPERMV3
llvm-svn: 284922
2016-10-22 20:15:39 +00:00
Simon Pilgrim 56c0524f0f [X86][AVX512] Added support for combining target shuffles to AVX512 VPERMV3
llvm-svn: 284921
2016-10-22 19:53:59 +00:00
James Molloy 2bae8640d7 [ARM] Fix crash in ConstantIslands
tPCRelJT may not be the first instruction in a block. Check that instead of dereferencing a broken iterator.

llvm-svn: 284917
2016-10-22 09:58:37 +00:00
Zvi Rackover 8eb99d88d4 [X86] Apply the Update LLC Test Checks tool on the mmx-bitcast test
llvm-svn: 284916
2016-10-22 07:15:00 +00:00
Craig Topper b084c90a18 [X86] Add support for printing shuffle comments for VALIGN instructions.
llvm-svn: 284915
2016-10-22 06:51:56 +00:00
Gerolf Hoflehner 9e2afa8bd7 [BasicAA] Fix - missed alias in GEP expressions
In BasicAA GEP operand values get adjusted ("wrap-around") based on the
pointersize. Otherwise, in non-64b modes, AA could report false negatives.
However, a wrap-around is valid only for a fully evaluated expression.
It had been introduced to fix an alias problem in
http://lists.llvm.org/pipermail/llvm-commits/Week-of-Mon-20160118/326163.html.
This commit restricts the wrap-around to constant gep operands only where the
value is known at compile-time.

llvm-svn: 284908
2016-10-22 02:41:39 +00:00
Sanjay Patel 5b7767f646 [x86] add test for missing vector SRA combine via computeKnownBits
llvm-svn: 284896
2016-10-21 23:02:31 +00:00
Tom Stellard 6c7dd980e4 AMDGPU/SI: Fix crash caused by r284267
Reviewers: arsenm, nhaehnle

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, tony-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D25782

llvm-svn: 284875
2016-10-21 20:25:11 +00:00
Sanjay Patel ca92c36e01 [DAG] enhance computeKnownBits to handle SHL with vector splat constant
Also, use APInt to avoid crashing on types larger than vNi64.

llvm-svn: 284874
2016-10-21 20:16:27 +00:00
Li Huang faa857dba7 [SCEV] Memoize visitMulExpr results in SCEVRewriteVisitor.
Summary:
When SCEVRewriteVisitor traverses the SCEV DAG, it may visit the same SCEV
multiple times if this SCEV is referenced by multiple other SCEVs. This has
exponential time complexity in the worst case. Memoizing the results will
avoid re-visiting the same SCEV. Add a map to save the results, and override
the visit function of SCEVVisitor. Now SCEVRewriteVisitor only visit each
SCEV once and thus returns the same result for the same input SCEV.

This patch fixes PR18606, PR18607.

Reviewers: Sanjoy Das, Mehdi Amini, Michael Zolotukhin

Differential Revision: https://reviews.llvm.org/D25810

llvm-svn: 284868
2016-10-21 20:05:21 +00:00
Kevin Enderby 2f9d8d0702 Fix a bug in the code of llvm-cxxdump in dumpArchive() when
iterating over an archive with object and non-object members that
would cause an Abort because to was not calling consumeError()
when the code was wanting to ignore a non-object file.

Found by Justin Bogner!

llvm-svn: 284867
2016-10-21 20:03:14 +00:00
Peter Collingbourne e9bd49824d X86: Improve BT instruction selection for 64-bit values.
If a 64-bit value is tested against a bit which is known to be in the range
[0..31) (modulo 64), we can use the 32-bit BT instruction, which has a slightly
shorter encoding.

Differential Revision: https://reviews.llvm.org/D25862

llvm-svn: 284864
2016-10-21 19:57:55 +00:00
Simon Pilgrim ab48872313 [X86][AVX512BWVL] Added support for lowering v16i16 shuffles to AVX512BWVL vpermw
llvm-svn: 284863
2016-10-21 19:54:38 +00:00
Bob Haarman 653baa2aaa [pdb] added support for dumping globals stream
Summary: This adds support for dumping the globals stream from PDB files using llvm-pdbdump, similar to the support we have for the publics stream.

Reviewers: ruiu, zturner

Subscribers: beanz, mgorny, modocache

Differential Revision: https://reviews.llvm.org/D25801

llvm-svn: 284861
2016-10-21 19:43:19 +00:00
Simon Pilgrim da814cba0d [X86][AVX512BWVL] Added support for combining target v16i16 shuffles to AVX512BWVL vpermw
llvm-svn: 284860
2016-10-21 19:40:29 +00:00
Simon Pilgrim 0109bf116f [X86][AVX512] Added support for combining target shuffles to AVX512 vpermpd/vpermq/vpermps/vpermd/vpermw
llvm-svn: 284858
2016-10-21 19:18:09 +00:00
Anna Thomas 0860259434 [StripGCRelocates] New pass to remove gc.relocates added by RS4GC
Summary:
Utility pass to remove gc.relocates created by rewrite statepoints for GC.
With respect to safepoint verification, the IR generated would be incorrect, and cannot run
as such.

This would be a single transformation on the final optimized IR.
The benefit of the pass is for easy analysis when the IRs are 'polluted' by too
many gc.relocates.
Added tests.

test run: All RS4GC tests with -verify option. Local downstream tests on large
IR files. This also works when the pointer being gc.relocated is another
gc.relocate.

Reviewers: sanjoy, reames

Subscribers: beanz, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D25096

llvm-svn: 284855
2016-10-21 18:43:16 +00:00
Kevin Enderby 41c9c00bf0 For llvm-objdump for Mach-O files add printing of
the ARM_THREAD_STATE in the same format as
otool-classic(1) on darwin.

Also remove an extra space in printing the initprot to make
the output match otool-classic(1) on darwin.

rdar://28851457

llvm-svn: 284852
2016-10-21 18:22:35 +00:00
Sanjay Patel 81029f6a76 [DAG] fold negation of sign-bit
0 - X --> 0, if the sub is NUW
0 - X --> 0, if X is 0 or the minimum signed value and the sub is NSW
0 - X --> X, if X is 0 or the minimum signed value

This is the DAG equivalent of:
https://reviews.llvm.org/rL284649

plus the fold for the NUW case which already existed in InstSimplify.

Note that we miss a vector fold because of a deficiency in the DAG version of
computeKnownBits().

llvm-svn: 284844
2016-10-21 17:24:26 +00:00
Sanjay Patel 97de8a4c3a [x86] add tests for potential negation folds
These are the backend equivalents for the tests added in r284627.
The patterns may emerge late, so we should have folds for these in the DAG too.

llvm-svn: 284842
2016-10-21 16:56:29 +00:00
Krzysztof Parzyszek b71085b547 [Hexagon] Handle spills of partially defined double vector registers
After register allocation it is possible to have a spill of a register
that is only partially defined. That in itself it fine, but creates a
problem for double vector registers. Stores of such registers are pseudo
instructions that are expanded into pairs of individual vector stores,
and in case of a partially defined source, one of the stores may use
an entirely undefined register. To avoid this, track the defined parts
and only generate actual stores for those.

llvm-svn: 284841
2016-10-21 16:38:29 +00:00
Derek Schuff 6f69783f1f [WebAssembly] Fix for 0xc call_indirect changes
Summary:
Need to reorder the operands to have the callee as the last argument.
Adds a pseudo-instruction, and a pass to lower it into a real
call_indirect.

This is the first of two options for how to fix the problem.

Reviewers: dschuff, sunfish

Subscribers: jfb, beanz, mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D25708

llvm-svn: 284840
2016-10-21 16:38:07 +00:00
Simon Pilgrim 372e916a3f [X86][SSE] Regenerated sext/zext constant folding tests and added i686 tests
llvm-svn: 284837
2016-10-21 16:22:16 +00:00
Simon Pilgrim 098bd72804 [X86][SSE] Regenerated chained pmovsx store tests and added i686 tests
llvm-svn: 284833
2016-10-21 15:51:24 +00:00
Artur Pilipenko 47dc098c06 [LVI] Fix a bug with a guard being the very first instruction in a BB not taken into account
While looking for guards use reverse iterator and scan up to rend() not to begin()

llvm-svn: 284827
2016-10-21 15:02:21 +00:00
Artem Tamazov 751985a757 [AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.
Fixes Bug 28215. Lit tests updated.

Differential Revision: https://reviews.llvm.org/D25837

llvm-svn: 284825
2016-10-21 14:49:22 +00:00
Sanjay Patel cbaba93ce8 [DAG] use SDNode flags 'nsz' to enable fadd/fsub with zero folds
As discussed in D24815, let's start the process of killing off the broken fast-math global
state housed in TargetOptions and eliminate the need for function-level fast-math attributes.

Here we enable two similar folds that are possible when we don't care about signed-zero:
fadd nsz x, 0 --> x
fsub nsz 0, x --> -x

Note that although the test cases include a 'sin' function call, I'm side-stepping the 
FMF-on-calls question (and lack of support in the DAG) for now. It's not needed for these
tests - isNegatibleForFree/GetNegatedExpression just look through a ISD::FSIN node.

Also, when we create an FNEG node and propagate the Flags of the FSUB to it, this doesn't
actually do anything today because Flags are silently dropped for any node that is not a
binary operator.

Differential Revision: https://reviews.llvm.org/D25297

llvm-svn: 284824
2016-10-21 14:36:58 +00:00
Simon Pilgrim 32b06235da [X86][AVX512] Add mask/maskz writemask support to subvector broadcast shuffle decode comments
llvm-svn: 284821
2016-10-21 12:14:24 +00:00
John Brawn 84b21835f1 [LoopUnroll] Keep the loop test only on the first iteration of max-or-zero loops
When we have a loop with a known upper bound on the number of iterations, and
furthermore know that either the number of iterations will be either exactly
that upper bound or zero, then we can fully unroll up to that upper bound
keeping only the first loop test to check for the zero iteration case.

Most of the work here is in plumbing this 'max-or-zero' information from the
part of scalar evolution where it's detected through to loop unrolling. I've
also gone for the safe default of 'false' everywhere but howManyLessThans which
could probably be improved.

Differential Revision: https://reviews.llvm.org/D25682

llvm-svn: 284818
2016-10-21 11:08:48 +00:00
Simon Pilgrim f447fbf913 [X86][AVX] Add 32-bit target tests for vector lzcnt/tzcnt to demonstrate missed folding opportunities
llvm-svn: 284816
2016-10-21 10:50:52 +00:00
Benjamin Kramer 0d41eb8cd1 Fix WebAssembly test after r284757.
The change to MachineSink shuffles code around, disable it.

llvm-svn: 284813
2016-10-21 09:51:41 +00:00
Craig Topper c1db0db864 [AVX-512] Add tests to show opportunities for commuting vpermi2/vpermt2 instructions.
Commuting will be added in a future commit.

llvm-svn: 284808
2016-10-21 05:55:40 +00:00
Davide Italiano d15477b09d Revert "[GVN/PRE] Hoist global values outside of loops."
There's no agreement about this patch. I personally find the
PRE machinery of the current GVN hard enough to reason about
that I'm not sure I'll try to land this again, instead of working
on the rewrite).

llvm-svn: 284796
2016-10-21 01:37:02 +00:00
Li Huang fcfe8cd3ae [SCEV] Add a threshold to restrict number of mul operands to be inlined into SCEV
This is to avoid inlining too many multiplication operands into a SCEV, which could 
take exponential time in the worst case.

Reviewers: Sanjoy Das, Mehdi Amini, Michael Zolotukhin

Differential Revision: https://reviews.llvm.org/D25794

llvm-svn: 284784
2016-10-20 21:38:39 +00:00
Keno Fischer c32ffe3916 Fix PREL31 relocation on ARM
Summary:
This is a 31bits relative relocation instead of a 32bits absolute relocation.

Reviewers: t.p.northover, peter.smith, rengolin

Subscribers: aemerson, llvm-commits, samparker

Differential Revision: https://reviews.llvm.org/D25069

llvm-svn: 284780
2016-10-20 21:15:29 +00:00
Michael Kuperstein b2443ed62b [X86] Enable interleaved memory access by default
This lets the loop vectorizer generate interleaved memory accesses on x86.

Differential Revision: https://reviews.llvm.org/D25350

llvm-svn: 284779
2016-10-20 21:04:31 +00:00
Kevin Enderby c8bb42283e Another additional error check for invalid Mach-O files for the
load commands that use the MachO::twolevel_hints_command type
which includes only the LC_TWOLEVEL_HINTS load command.

This is not used in llvm libObject code or in llvm tool code.  But
does appear in one of the binary test files.  While this load command is
obsolete it is easier to add code for it in libObject than edit or change
the binary test case.

llvm-svn: 284769
2016-10-20 20:10:30 +00:00
Konstantin Zhuravlyov 08326b6256 [AMDGPU] Emit constant address space data in .rodata section and use relocations instead of fixups (amdhsa only)
Differential Revision: https://reviews.llvm.org/D25693

llvm-svn: 284759
2016-10-20 18:12:38 +00:00
Dehao Chen f03f51555a Using branch probability to guide critical edge splitting.
Summary:
The original heuristic to break critical edge during machine sink is relatively conservertive: when there is only one instruction sinkable to the critical edge, it is likely that the machine sink pass will not break the critical edge. This leads to many speculative instructions executed at runtime. However, with profile info, we could model the splitting benefits: if the critical edge has 50% taken rate, it would always be beneficial to split the critical edge to avoid the speculated runtime instructions. This patch uses profile to guide critical edge splitting in machine sink pass.

The performance impact on speccpu2006 on Intel sandybridge machines:

spec/2006/fp/C++/444.namd                  25.3  +0.26%
spec/2006/fp/C++/447.dealII               45.96  -0.10%
spec/2006/fp/C++/450.soplex               41.97  +1.49%
spec/2006/fp/C++/453.povray               36.83  -0.96%
spec/2006/fp/C/433.milc                   23.81  +0.32%
spec/2006/fp/C/470.lbm                    41.17  +0.34%
spec/2006/fp/C/482.sphinx3                48.13  +0.69%
spec/2006/int/C++/471.omnetpp             22.45  +3.25%
spec/2006/int/C++/473.astar               21.35  -2.06%
spec/2006/int/C++/483.xalancbmk           36.02  -2.39%
spec/2006/int/C/400.perlbench              33.7  -0.17%
spec/2006/int/C/401.bzip2                  22.9  +0.52%
spec/2006/int/C/403.gcc                   32.42  -0.54%
spec/2006/int/C/429.mcf                   39.59  +0.19%
spec/2006/int/C/445.gobmk                 26.98  -0.00%
spec/2006/int/C/456.hmmer                 24.52  -0.18%
spec/2006/int/C/458.sjeng                 28.26  +0.02%
spec/2006/int/C/462.libquantum            55.44  +3.74%
spec/2006/int/C/464.h264ref               46.67  -0.39%

geometric mean                                   +0.20%

Manually checked 473 and 471 to verify the diff is in the noise range.

Reviewers: rengolin, davidxl

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D24818

llvm-svn: 284757
2016-10-20 18:06:52 +00:00
Simon Pilgrim 365be4f95c [CostModel][X86] Fixed AVX1/AVX512 sdiv/udiv uniformconst costs for 256/512 bit integer vectors
We weren't checking for uniform const costs before the general cost, resulting in very high estimates.

llvm-svn: 284755
2016-10-20 18:00:35 +00:00
Pirama Arumuga Nainar 05b0f93ad3 Fix *_EXTEND_VECTOR_INREG legalization
Summary:
While promoting *_EXTEND_VECTOR_INREG nodes whose inputs are already
promoted, perform the appropriate sign extension for the promoted node
before doing the *_EXTEND_VECTOR_INREG operation.  If not, the undefined
high-order bits of the promoted operand may (a) be garbage inc ase of
zext) or (b) contribute the wrong sign-bit (in case of sext)

Updated the promote-vec3.ll test after this change.  The diff shows
explicit zeroing in case of zext and intermediate sign extension in case
of sext.

Reviewers: RKSimon

Subscribers: llvm-commits, srhines

Differential Revision: https://reviews.llvm.org/D25790

llvm-svn: 284752
2016-10-20 17:56:36 +00:00
Simon Pilgrim 1388c0acc1 [CostModel][X86] Added tests for sdiv/udiv costs for uniform const and uniform const power-of-2
Shows poor costings in AVX1/AVX512BW for certain vector types

llvm-svn: 284748
2016-10-20 17:16:38 +00:00