Commit Graph

277180 Commits

Author SHA1 Message Date
Rafael Espindola f70502d3a6 Bring r319051 back.
It had been reverted because it depended on r319008 which has been
recommitted.

Original message:

Add a missing test.

We were not testing that we correctly handled a .o with a weak symbol
after a .so.

llvm-svn: 319217
2017-11-28 20:21:44 +00:00
Daniel Sanders 7fe7acc6b1 [aarch64][globalisel] Define G_ATOMIC_CMPXCHG and G_ATOMICRMW_* and make them legal
The IRTranslator cannot generate these instructions at the moment so there's no
issue with not having implemented ISel for them yet. D40092 will add
G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMICRMW_* to the IRTranslator and a
further patch will add support for lowering G_ATOMIC_CMPXCHG_WITH_SUCCESS into
G_ATOMIC_CMPXCHG with an external success check via the `Lower` action.

The separation of G_ATOMIC_CMPXCHG_WITH_SUCCESS and G_ATOMIC_CMPXCHG is
to import SelectionDAG rules while still supporting targets that prefer to
custom lower the original LLVM-IR-like operation.

llvm-svn: 319216
2017-11-28 20:21:15 +00:00
Rafael Espindola 1d4b3023dc Bring back r319008.
This includes a fix to mark copy reloc aliases as used.

Original message:

[ELF] Do not keep symbols if they referenced only from discarded sections.

This patch also ensures that in case of "--as-needed" is used,
DT_NEEDED entries are not created if they are required only by
these eliminated symbols.

llvm-svn: 319215
2017-11-28 20:17:58 +00:00
Rafael Espindola 57ef60f0f9 Add missing test.
This would have found the issue with r319008.

llvm-svn: 319214
2017-11-28 20:13:12 +00:00
Greg Clayton 7547aca722 Update remote debugging page with many more details.
llvm-svn: 319213
2017-11-28 20:04:43 +00:00
Rui Ueyama 28c65bc20b Fix formatting.
llvm-svn: 319212
2017-11-28 20:01:30 +00:00
Rui Ueyama 3e03944f02 Factor out more code to Common/Args.cpp.
Differential Revision: https://reviews.llvm.org/D40540

llvm-svn: 319211
2017-11-28 19:58:45 +00:00
Mandeep Singh Grang 230b0a1477 [SelectionDAG] Make sorting predicate stronger to remove non-deterministic ordering
Summary:
Recommitting this with the correct sorting predicate. The Low field of Clusters is a ConstantInt and
cannot be directly compared. So we needed to invoke slt (signed less than) to compare correctly.

This fixes failures in the following tests uncovered by D39245:

LLVM :: CodeGen/ARM/ifcvt3.ll
LLVM :: CodeGen/ARM/switch-minsize.ll
LLVM :: CodeGen/X86/switch.ll
LLVM :: CodeGen/X86/switch-bt.ll
LLVM :: CodeGen/X86/switch-density.ll

Reviewers: hans, fhahn

Reviewed By: hans

Subscribers: aemerson, llvm-commits, kristof.beyls

Differential Revision: https://reviews.llvm.org/D40541

llvm-svn: 319210
2017-11-28 19:55:54 +00:00
Simon Pilgrim d49bd0cd87 [X86][SSE] Add SSE_HADDSUB/SSE_PABS/SSE_PALIGN OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it.

Will be reused in the AVX512 equivalents.

llvm-svn: 319209
2017-11-28 19:39:47 +00:00
Craig Topper dd4295626b [X86] In lowerVectorShuffleAsElementInsertion, if were able to find a scalar i8 or i16 and need to zero extend it, make sure we use a vXi32 type of the full vector width.
Previously, this was hardcoded to v4i32, but if the input type is 256 bits we need to use v8i32.

Fixes PR35443

llvm-svn: 319208
2017-11-28 19:25:45 +00:00
Francis Visoiu Mistrih 3aa8eaa951 [CodeGen] Fix doxygen \file comment style
llvm-svn: 319207
2017-11-28 19:23:39 +00:00
Francis Visoiu Mistrih d4b340b460 [CodeGen] Fix doxygen
llvm-svn: 319206
2017-11-28 19:15:46 +00:00
Sanjay Patel 1a72f67006 [InstCombine] auto-generate complete test checks; NFC
llvm-svn: 319205
2017-11-28 19:13:23 +00:00
Krzysztof Parzyszek 081e458e90 [Hexagon] Make sure to zero-extend bytes before building a vector
llvm-svn: 319204
2017-11-28 19:13:17 +00:00
Sanjay Patel b1a97d3774 [InstCombine] auto-generate complete test checks; NFC
llvm-svn: 319203
2017-11-28 19:07:28 +00:00
Daniel Sanders 17d277b734 [mir] Print/Parse both MOLoad and MOStore when they occur together.
Summary:
They're not always mutually exclusive. read-modify-write atomics are both
at the same time. One example of this is the SWP instructions on AArch64.
Another example is GlobalISel's G_ATOMICRMW_* generic instructions which
will be added in a later patch.

Reviewers: arphaman, aemerson

Reviewed By: aemerson

Subscribers: aemerson, javed.absar, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D40157

llvm-svn: 319202
2017-11-28 18:57:02 +00:00
Artem Belevich 50e6e54587 [CUDA] Report "unsupported VLA" errors only on device side.
This fixes erroneously reported CUDA compilation errors
in host-side code during device-side compilation.

I've also restricted OpenMP-specific checks to trigger only
if we're compiling with OpenMP enabled.

Differential Revision: https://reviews.llvm.org/D40275

llvm-svn: 319201
2017-11-28 18:51:42 +00:00
Rafael Espindola bba7f862d8 Fix non assert build warnings.
llvm-svn: 319200
2017-11-28 18:50:08 +00:00
Hans Wennborg ca46db957d EntryExitInstrumenter: set DebugLocs on the inserted call instructions (PR35412)
Apparently the verifier requires that inlineable calls in a function
with debug info have debug locations.

llvm-svn: 319199
2017-11-28 18:44:26 +00:00
Zachary Turner 6900de1dfb [CodeView] Refactor / Rewrite TypeSerializer and TypeTableBuilder.
The motivation behind this patch is that future directions require us to
be able to compute the hash value of records independently of actually
using them for de-duplication.

The current structure of TypeSerializer / TypeTableBuilder being a
single entry point that takes an unserialized type record, and then
hashes and de-duplicates it is not flexible enough to allow this.

At the same time, the existing TypeSerializer is already extremely
complex for this very reason -- it tries to be too many things. In
addition to serializing, hashing, and de-duplicating, ti also supports
splitting up field list records and adding continuations. All of this
functionality crammed into this one class makes it very complicated to
work with and hard to maintain.

To solve all of these problems, I've re-written everything from scratch
and split the functionality into separate pieces that can easily be
reused. The end result is that one class TypeSerializer is turned into 3
new classes SimpleTypeSerializer, ContinuationRecordBuilder, and
TypeTableBuilder, each of which in isolation is simple and
straightforward.

A quick summary of these new classes and their responsibilities are:

- SimpleTypeSerializer : Turns a non-FieldList leaf type into a series of
  bytes. Does not do any hashing. Every time you call it, it will
  re-serialize and return bytes again. The same instance can be re-used
  over and over to avoid re-allocations, and in exchange for this
  optimization the bytes returned by the serializer only live until the
  caller attempts to serialize a new record.

- ContinuationRecordBuilder : Turns a FieldList-like record into a series
  of fragments. Does not do any hashing. Like SimpleTypeSerializer,
  returns references to privately owned bytes, so the storage is
  invalidated as soon as the caller tries to re-use the instance. Works
  equally well for LF_FIELDLIST as it does for LF_METHODLIST, solving a
  long-standing theoretical limitation of the previous implementation.

- TypeTableBuilder : Accepts sequences of bytes that the user has already
  serialized, and inserts them by de-duplicating with a hash table. For
  the sake of convenience and efficiency, this class internally stores a
  SimpleTypeSerializer so that it can accept unserialized records. The
  same is not true of ContinuationRecordBuilder. The user is required to
  create their own instance of ContinuationRecordBuilder.

Differential Revision: https://reviews.llvm.org/D40518

llvm-svn: 319198
2017-11-28 18:33:17 +00:00
Simon Pilgrim 4fecbd8871 [X86][X87] Tag FP_TO_INT_IN_MEM pseudos with hasNoSchedulingInfo
We don't need scheduling info for pseudos

llvm-svn: 319197
2017-11-28 18:10:29 +00:00
Rafael Espindola b45c164fc2 Handle binding in --wrap.
Copying the binding seems reasonable and matches the bfd behavior.

llvm-svn: 319196
2017-11-28 18:02:22 +00:00
Craig Topper b338400188 [Target] Make a copy of TargetOptions feature list before sorting during CodeGen
Currently CodeGen is calling std::sort on the features vector in TargetOptions for every function, but I don't think CodeGen should be modifying TargetOptions.

Differential Revision: https://reviews.llvm.org/D40228

llvm-svn: 319195
2017-11-28 18:00:32 +00:00
Francis Visoiu Mistrih aa739695a4 [CodeGen] Separate MachineOperand implementation from MachineInstr
Move the implementation to its own file.

Differential Revision: https://reviews.llvm.org/D40419

llvm-svn: 319194
2017-11-28 17:58:43 +00:00
Francis Visoiu Mistrih 946e394e33 [CodeGen] Cleanup MachineOperand
* clang-format
* move doxygen from the implementation to headers
* remove duplicate doxygen

llvm-svn: 319193
2017-11-28 17:58:38 +00:00
Konstantin Zhuravlyov 06ae4ec78e AMDGPU: Add num spilled s/vgprs to metadata
This was requested by tools.

Differential Revision: https://reviews.llvm.org/D40321

llvm-svn: 319192
2017-11-28 17:51:08 +00:00
Stephane Sezer 5011298958 Simplify UUID constructors
Summary: This remove a small amount of duplicated code.

Reviewers: clayborg, zturner, davide

Subscribers: lldb-commits

Differential Revision: https://reviews.llvm.org/D40536

llvm-svn: 319191
2017-11-28 17:50:31 +00:00
Dan Liew 37516b527b [LibFuzzer] Improve comments on `CounterToFeature()` function.
This is based on discussion in https://reviews.llvm.org/D40376 .

The comments try to explain the reason for the current implementation
and note that it might change in the future, so clients should not
rely on this particular implementation.

Differential Revision: https://reviews.llvm.org/D40565

llvm-svn: 319190
2017-11-28 17:41:58 +00:00
Kamil Rytarowski 4e9e9bf0cf Support the setjmp(3) family of functions in TSan/NetBSD
Summary:
This change adds support for the setjmp(3)/longjmp(3)
family of functions on NetBSD.

There are three types of them on NetBSD:

 - setjmp(3) / longjmp(3)
 - sigsetjmp(3) / sigsetjmp(3)
 - _setjmp(3) / _longjmp(3)

Due to historical and compat reasons the symbol
names are mangled:

 - setjmp -> __setjmp14
 - longjmp -> __longjmp14
 - sigsetjmp -> __sigsetjmp14
 - siglongjmp -> __siglongjmp14
 - _setjmp -> _setjmp
 - _longjmp -> _longjmp

This leads to symbol renaming in the existing codebase.

There is no such symbol as __sigsetjmp/__longsetjmp
on NetBSD

Add a comment that GNU-style executable stack
note is not needed on NetBSD. The stack is not
executable without it.

Sponsored by <The NetBSD Foundation>

Reviewers: joerg, dvyukov, vitalybuka

Reviewed By: dvyukov

Subscribers: llvm-commits, kubamracek, #sanitizers

Tags: #sanitizers

Differential Revision: https://reviews.llvm.org/D40337

llvm-svn: 319189
2017-11-28 17:35:35 +00:00
Adam Nemet 353f7cbc21 Add opt-viewer testing
Detects whether we have the Python modules (pygments, yaml) required by
opt-viewer and hooks this up to REQUIRES.

This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer
testing).

It's also related to https://github.com/apple/swift/pull/12938 and the idea is
to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake.

Differential Revision: https://reviews.llvm.org/D40202

llvm-svn: 319188
2017-11-28 17:26:28 +00:00
Francis Visoiu Mistrih 9d7bb0cb40 [CodeGen] Print register names in lowercase in both MIR and debug output
As part of the unification of the debug format and the MIR format,
always print registers as lowercase.

* Only debug printing is affected. It now follows MIR.

Differential Revision: https://reviews.llvm.org/D40417

llvm-svn: 319187
2017-11-28 17:15:09 +00:00
Dan Gohman 2803bfaf00 [WebAssembly] Support bitcasted function addresses with varargs.
Generalize FixFunctionBitcasts to handle varargs functions. This in
particular fixes the case where clang bitcasts away a varargs when
calling a K&R-style function.

This avoids interacting with tricky ABI details because it operates
at the LLVM IR level before varargs ABI details are exposed.

This fixes PR35385.

llvm-svn: 319186
2017-11-28 17:15:03 +00:00
Matt Arsenault e123aba94e DAG: Legalize truncstores to illegal int types
Truncate to a legal int type, and produce a new
truncstore from a narrower type.

llvm-svn: 319185
2017-11-28 17:11:30 +00:00
Simon Pilgrim ece5bc358a [X86][X87] Tag FTST x87 instruction scheduler class
Looking through Agner, FTST is very similar to generic float compare behaviour, so I've added them to the existing IIC_FCOMI (WriteFAdd) tags.

llvm-svn: 319184
2017-11-28 16:57:20 +00:00
Alexander Kornienko 1bfcba8cea [clang-tidy] Move more checks from misc- to performance-
Summary:
rename_check.py misc-move-const-arg performance-move-const-arg
rename_check.py misc-noexcept-move-constructor performance-noexcept-move-constructor

Reviewers: hokein, xazax.hun

Reviewed By: xazax.hun

Subscribers: rnkovacs, klimek, mgorny, xazax.hun, cfe-commits

Differential Revision: https://reviews.llvm.org/D40507

llvm-svn: 319183
2017-11-28 16:41:03 +00:00
Sanjay Patel 14230e02ff [InstCombine] add tests from D39421 to show current transforms; NFC
llvm-svn: 319182
2017-11-28 16:40:30 +00:00
Bill Seurer 785294d497 [PowerPC][tsan] Update tsan to handle changed memory layouts in newer kernels
In more recent Linux kernels with 47 bit VMAs the layout of virtual memory
for powerpc64 changed causing the thread sanitizer to not work properly. This
patch adds support for 47 bit VMA kernels for powerpc64.

(second part)

Tested on several 4.x and 3.x kernel releases.

llvm-svn: 319180
2017-11-28 16:28:54 +00:00
Serge Pavlov 03e672ccab Refactor functions PrintTemplateArgumentList
These functions were defined as static members of TemplateSpecializationType.
Now they are moved to namespace level. Previously there were different
implementations for lists containing TemplateArgument and TemplateArgumentLoc,
now these implementations share the same code.

This change is a result of refactoring patch D40508. NFC.

llvm-svn: 319178
2017-11-28 16:14:14 +00:00
Francis Visoiu Mistrih 14bd3b9f21 [Support] Add unit test for printLowerCase
Add test case for the function added in r319171.

llvm-svn: 319177
2017-11-28 16:11:56 +00:00
Don Hinton 17fdf32cc1 [cmake] Remove redundant call to cmake when building host tools.
Summary:
Remove the redundant, config-time call to cmake when
building host tools for cross compiles or optimized tablegen..

The config-time call to cmake is redundant because it will always get
called again when the CONFIGURE_LLVM_${target_name} target fires at
build-time.  This speeds up initial configuration, but has no affect
on build behavior.

Reviewers: beanz

Reviewed By: beanz

Subscribers: mgorny, llvm-commits

Differential Revision: https://reviews.llvm.org/D40229

llvm-svn: 319176
2017-11-28 16:08:57 +00:00
Simon Pilgrim 0747a7e8c3 [X86][X87] Tag FABS/FCHS/FSQRT/FSIN/FCOS x87 instruction scheduler classes
Atom's FABS/FCHS/FSQRT latencies taken from Agner.

Note: I just added FSIN and FCOS to the existing IIC_FSINCOS itinerary, which is actually a more costly instruction.
llvm-svn: 319175
2017-11-28 15:03:42 +00:00
Malcolm Parsons 91e2c2addc [clang-tidy] Ignore ExprWithCleanups when looking for else-after-throw
Summary:
The readability-else-after-return check was not warning about
an else after a throw of an exception that had arguments that needed
to be cleaned up.

Reviewers: aaron.ballman, alexfh, djasper

Reviewed By: aaron.ballman

Subscribers: lebedev.ri, klimek, xazax.hun, cfe-commits

Differential Revision: https://reviews.llvm.org/D40505

llvm-svn: 319174
2017-11-28 14:57:47 +00:00
Jonas Paulsson f0ff20f1f0 Use getStoreSize() in various places instead of 'BitSize >> 3'.
This is needed for cases when the memory access is not as big as the width of
the data type. For instance, storing i1 (1 bit) would be done in a byte (8
bits).

Using 'BitSize >> 3' (or '/ 8') would e.g. give the memory access of an i1 a
size of 0, which for instance makes alias analysis return NoAlias even when
it shouldn't.

There are no tests as this was done as a follow-up to the bugfix for the case
where this was discovered (r318824). This handles more similar cases.

Review: Björn Petterson
https://reviews.llvm.org/D40339

llvm-svn: 319173
2017-11-28 14:44:32 +00:00
Simon Pilgrim b843dc26e4 [X86][X86] Add some x87 schedule tests
Still missing some instructions: mainly loads/stores/system ops, all flagged as TODO.

llvm-svn: 319172
2017-11-28 14:35:52 +00:00
Francis Visoiu Mistrih 26d6fc1f0e [Support] Merge toLower / toUpper implementations
Merge the ones from StringRef and StringExtras.

llvm-svn: 319171
2017-11-28 14:22:27 +00:00
Gabor Horvath 61d39595b4 [clang-tidy] Fix tests for ReplaceRandomShuffleCheck
Patch by: Daniel Kolozsvari!

Differential Revision: https://reviews.llvm.org/D40516

llvm-svn: 319170
2017-11-28 13:54:52 +00:00
Peter Smith 57eb046984 [ELF] Read ARM BuildAttributes section to determine supported features.
lld assumes some ARM features that are not available in all Arm
processors. In particular:
- The blx instruction present for interworking.
- The movt/movw instructions are used in Thunks.
- The J1=1 J2=1 encoding of branch immediates to improve Thumb wide
  branch range are assumed to be present.

This patch reads the ARM Attributes section to check for the
architecture the object file was compiled with. If none of the objects
have an architecture that supports either of these features a warning
will be given. This is most likely to affect armv6 as used in the first
Raspberry Pi.

Differential Revision: https://reviews.llvm.org/D36823

llvm-svn: 319169
2017-11-28 13:51:48 +00:00
Francis Visoiu Mistrih 9d419d3b0c [CodeGen] Rename functions PrintReg* to printReg*
LLVM Coding Standards:
  Function names should be verb phrases (as they represent actions), and
  command-like function should be imperative. The name should be camel
  case, and start with a lower case letter (e.g. openFile() or isFoo()).

Differential Revision: https://reviews.llvm.org/D40416

llvm-svn: 319168
2017-11-28 12:42:37 +00:00
Simon Pilgrim 8dc603b031 [X86][3DNow] Add instruction itinerary and scheduling classes for femms/prefetch/prefetchw
llvm-svn: 319167
2017-11-28 12:37:35 +00:00
Peter Smith a939257a42 [ARM][AArch64] Workaround ARM/AArch64 peculiarity in clearing icache.
Certain ARM implementations treat icache clear instruction as a memory read,
and CPU segfaults on trying to clear cache on !PROT_READ page.
We workaround this in Memory::protectMappedMemory by adding
PROT_READ to affected pages, clearing the cache, and then setting
desired protection.

This fixes "AllocationTests/MappedMemoryTest.***/3" unit-tests on
affected hardware.

Reviewers: psmith, zatrazz, kristof.beyls, lhames

Reviewed By: lhames

Subscribers: llvm-commits, krytarowski, peter.smith, jgreenhalgh, aemerson,
             rengolin

Patch by maxim-kuvrykov! 

Differential Revision: https://reviews.llvm.org/D40423

llvm-svn: 319166
2017-11-28 12:34:05 +00:00