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901 Commits

Author SHA1 Message Date
Matt Arsenault 46b51b7f62 R600: Add definition for flat address space ID. 
Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.

llvm-svn: 209463
 2014-05-22 18:27:07 +00:00
Matt Arsenault 05e96f4444 R600: Try to convert BFE back to standard bit ops when possible. 
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

llvm-svn: 209462
 2014-05-22 18:09:12 +00:00
Matt Arsenault 5565f65e13 R600: Add dag combine for BFE 
llvm-svn: 209461
 2014-05-22 18:09:07 +00:00
Matt Arsenault bf8694d36d R600: Implement ComputeNumSignBitsForTargetNode for BFE 
llvm-svn: 209460
 2014-05-22 18:09:03 +00:00
Matt Arsenault af6df9d943 R600: Implement computeMaskedBitsForTargetNode for BFE 
llvm-svn: 209459
 2014-05-22 18:09:00 +00:00
Matt Arsenault 493c5f1bc4 R600: Expand mul24 for GPUs without it 
llvm-svn: 209458
 2014-05-22 18:00:24 +00:00
Matt Arsenault f15a05623e R600: Expand mad24 for GPUs without it 
llvm-svn: 209457
 2014-05-22 18:00:20 +00:00
Matt Arsenault eb260206c3 R600: Add intrinsics for mad24 
llvm-svn: 209456
 2014-05-22 18:00:15 +00:00
Matt Arsenault f37abc71de R600/SI: Move instruction pattern to instruction definition 
llvm-svn: 209454
 2014-05-22 17:45:20 +00:00
Matt Arsenault c3a73c3087 R600/SI: Match fp_to_uint / uint_to_fp for f64 
llvm-svn: 209388
 2014-05-22 03:20:30 +00:00
Matt Arsenault 40100887b6 R600: Add comment describing problems with LowerConstantInitializer 
llvm-svn: 209333
 2014-05-21 22:59:17 +00:00
Matt Arsenault 6a57fd8b47 R600: Partially fix constant initializers for structs and vectors. 
This should extend the current workaround to work with structs
that only contain legal, scalar types.

llvm-svn: 209331
 2014-05-21 22:42:42 +00:00
Matt Arsenault 03df7eeda1 Use cast<> instead of unchecked dyn_cast 
llvm-svn: 209310
 2014-05-21 18:03:59 +00:00
Matt Arsenault 0a3b8f5507 Remove unused method declaration 
llvm-svn: 209174
 2014-05-19 22:55:35 +00:00
Aaron Ballman 0dfed533ec Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended. 
llvm-svn: 209126
 2014-05-19 14:29:04 +00:00
Tom Stellard c721a23882 R600/SI: Refactor the VOP3_32 tablegen class 
This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.

llvm-svn: 209028
 2014-05-16 20:56:47 +00:00
Tom Stellard 0e70de57a3 R600/SI: Add a PredicateControl class for managing TableGen predicates 
This was inspired by the PredicateControl class in the MIPS backend.

llvm-svn: 209027
 2014-05-16 20:56:45 +00:00
Tom Stellard 0289ff4a4f R600/SI: Move tablegen patterns away from instruction defs 
llvm-svn: 209026
 2014-05-16 20:56:44 +00:00
Tom Stellard 2671338497 R600/SI: Remove unused instruction 
llvm-svn: 209025
 2014-05-16 20:56:43 +00:00
Tom Stellard f719ee9e76 R600/SI: Promote f32 SELECT to i32 
llvm-svn: 209024
 2014-05-16 20:56:41 +00:00
Tom Stellard 725db5d2c8 R600/SI: Remove duplicate pattern 
llvm-svn: 209023
 2014-05-16 20:56:37 +00:00
Matt Arsenault d504a74e3c Use range for 
llvm-svn: 208922
 2014-05-15 21:44:05 +00:00
Tom Stellard 436780bebb R600/SI: Stop using VSrc_* as the default register class for types. 
We now use SReg_* for integer types and VReg_* for floating-point types.
This should help simplify the SIFixSGPRCopies pass and no longer causes
ISel to insert a COPY after termiator instuctions that output a value.

This change is covered by exisitng tests.

llvm-svn: 208888
 2014-05-15 14:41:57 +00:00
Tom Stellard a568738b47 R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies 
This prevents a future commit from regressing the load-i1.ll test.

llvm-svn: 208887
 2014-05-15 14:41:55 +00:00
Tom Stellard 73b98ed8cf R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0 
llvm-svn: 208886
 2014-05-15 14:41:54 +00:00
Tom Stellard 365a2b49f2 R600/SI: Use VALU instructions for i1 ops 
llvm-svn: 208885
 2014-05-15 14:41:50 +00:00
Jay Foad a0653a3e6c Rename ComputeMaskedBits to computeKnownBits. "Masked" has been 
inappropriate since it lost its Mask parameter in r154011.

llvm-svn: 208811
 2014-05-14 21:14:37 +00:00
Matt Arsenault 4b0402e317 R600/SI: Try to fix BFE operands when moving to VALU 
This was broken by r208479

llvm-svn: 208740
 2014-05-13 23:45:50 +00:00
Matt Arsenault 37c12d7343 Use cast<> for unchecked use 
llvm-svn: 208627
 2014-05-12 20:42:57 +00:00
Matt Arsenault b3ee388594 Use cast<> for unchecked use 
llvm-svn: 208618
 2014-05-12 19:26:38 +00:00
Matt Arsenault 4d64f96530 Use range for 
llvm-svn: 208617
 2014-05-12 19:23:21 +00:00
Matt Arsenault 62b1737081 R600: Add mul24 intrinsics 
llvm-svn: 208604
 2014-05-12 17:49:57 +00:00
Matt Arsenault 46013d903f Fix return before else 
llvm-svn: 208510
 2014-05-11 21:24:41 +00:00
Vincent Lejeune 29c0c210fc R600/SI: Fold fabs/fneg into src input modifier 
llvm-svn: 208480
 2014-05-10 19:18:39 +00:00
Vincent Lejeune 94af31fbe8 R600/SI: Prettier display of input modifiers 
llvm-svn: 208479
 2014-05-10 19:18:33 +00:00
Vincent Lejeune 79a5834647 R600/SI: Use pseudo instruction for fabs/clamp/fneg 
llvm-svn: 208478
 2014-05-10 19:18:25 +00:00
Tom Stellard 4c00b52e1a R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructions 
llvm-svn: 208432
 2014-05-09 16:42:22 +00:00
Tom Stellard d6cb8e8efd R600/SI: Fix SMRD pattern for offsets > 32 bits 
We were dropping the high bits of 64-bit immediate offsets.

llvm-svn: 208431
 2014-05-09 16:42:21 +00:00
Tom Stellard a2acad785a R600: Expand i64 SELECT_CC 
llvm-svn: 208430
 2014-05-09 16:42:19 +00:00
Tom Stellard afa8b532b1 R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine() 
llvm-svn: 208429
 2014-05-09 16:42:16 +00:00
Matt Arsenault e8a076a253 R600: Promote f64 vector load/stores to i64 for consistency 
llvm-svn: 208344
 2014-05-08 18:01:56 +00:00
Tom Stellard 45b3dcd35b R600: Expand i64 ISD:SUB 
llvm-svn: 208005
 2014-05-05 21:47:15 +00:00
Marek Olsak 82d3b11e85 R600/SI: allow 5 more input SGPRs to a shader 
Our OpenGL driver needs 22 SGPRs (16 user SGPRs + 6 streamout non-user SGPRs).

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 207990
 2014-05-05 19:30:54 +00:00
Tom Stellard 10b1502733 R600/SI: Add processor type for Mullins. 
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
llvm-svn: 207846
 2014-05-02 15:41:49 +00:00
Tom Stellard 3dbf1f8df0 R600: Expand vector sin and cos. 
v2: move code to AMDGPUISelLowering.cpp
    squash with tests (both EG and SI)

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 207845
 2014-05-02 15:41:47 +00:00
Tom Stellard 605e116e8e R600: Expand TruncStore i64 -> {i16,i8} 
llvm-svn: 207844
 2014-05-02 15:41:46 +00:00
Tom Stellard eba61071d7 R600/SI: Only create one instruction when spilling/restoring register v3 
The register spiller assumes that only one new instruction is created
when spilling and restoring registers, so we need to emit pseudo
instructions for vector register spills and lower them after
register allocation.

v2:
  - Fix calculation of lane index
  - Extend VGPR liveness to end of program.

v3:
  - Use SIMM16 field of S_NOP to specify multiple NOPs.

https://bugs.freedesktop.org/show_bug.cgi?id=75005

llvm-svn: 207843
 2014-05-02 15:41:42 +00:00
Matt Arsenault 06028dd7be R600/SI: Fix verifier error with pseudo store instructions. 
Use i32 instead of specifying SReg_32. When this is
the pseudo INDIRECT_BASE_ADDR, this would give a bogus
verifier error.

llvm-svn: 207770
 2014-05-01 16:37:52 +00:00
Tom Stellard 1bd80725b3 R600/SI: Use VALU instructions for copying i1 values 
We can't use SALU instructions for this since they ignore the EXEC mask
and are always executed.

This fixes several OpenCV tests.

llvm-svn: 207661
 2014-04-30 15:31:33 +00:00
Tom Stellard 0c354f25c9 R600/SI: Teach moveToVALU how to handle some SMRD instructions 
llvm-svn: 207660
 2014-04-30 15:31:29 +00:00