Commit Graph

288156 Commits

Author SHA1 Message Date
Paul Walker f6e44a0bdf Fix typo in static_assert for size of LoadSDNodeBitfields.
Reviewers: fhahn, jlebar, delena, RKSimon

Reviewed By: fhahn, jlebar

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45769

llvm-svn: 330830
2018-04-25 14:42:44 +00:00
Filipe Cabecinhas def742ca52 [llvm-mca] Make ViewOptions static. NFCI
llvm-svn: 330829
2018-04-25 14:39:16 +00:00
Marshall Clow 3df56fdd9b Fix static initialization of std::atomic_flag; Fixes PR#37226. Thanks to Ricky Zhou for the report and test case.
llvm-svn: 330828
2018-04-25 14:27:29 +00:00
Shiva Chen d58bd8dc4a [RISCV] Expand function call to "call" pseudoinstruction
To do this:
1. Change GlobalAddress SDNode to TargetGlobalAddress to avoid legalizer
   split the symbol.

2. Change ExternalSymbol SDNode to TargetExternalSymbol to avoid legalizer
   split the symbol.

3. Let PseudoCALL match direct call with target operand TargetGlobalAddress
   and TargetExternalSymbol.

Differential Revision: https://reviews.llvm.org/D44885

llvm-svn: 330827
2018-04-25 14:19:12 +00:00
Shiva Chen 98f9389f65 [RISCV] Support "call" pseudoinstruction in the MC layer
To do this:
1. Add PseudoCALLIndirct to match indirect function call.

2. Add PseudoCALL to support parsing and print pseudo `call` in assembly

3. Expand PseudoCALL to the following form with R_RISCV_CALL relocation type
   while encoding:
        auipc ra, func
        jalr ra, ra, 0

If we expand PseudoCALL before emitting assembly, we will see auipc and jalr
pair when compile with -S. It's hard for assembly parser to parsing this
pair and identify it's semantic is function call and then insert R_RISCV_CALL
relocation type. Although we could insert R_RISCV_PCREL_HI20 and
R_RISCV_PCREL_LO12_I relocation types instead of R_RISCV_CALL.
Due to RISCV relocation design, auipc and jalr pair only can relax to jal with
R_RISCV_CALL + R_RISCV_RELAX relocation types.

We expand PseudoCALL as late as encoding(RISCVMCCodeEmitter) instead of before
emitting assembly(RISCVAsmPrinter) because we want to preserve call
pseudoinstruction in assembly code. It's more readable and assembly parser
could identify call assembly and insert R_RISCV_CALL relocation type.

Differential Revision: https://reviews.llvm.org/D45859

llvm-svn: 330826
2018-04-25 14:18:55 +00:00
Simon Dardis 0f2f5976d0 [mips] Teach the delay slot filler to transform 'jal' for microMIPS
ISel is currently picking 'JAL' over 'JAL_MM' for calling a function when
targeting microMIPS. A later patch will correct this behaviour.

This patch extends the mechanism for transforming instructions into their short
delay to recognise 'JAL_MM' for transforming into 'JALS_MM'.

llvm-svn: 330825
2018-04-25 14:12:57 +00:00
Yaxun Liu 9061e4f486 [HIP] Add predefined macros __HIPCC__ and __HIP_DEVICE_COMPILE__
Differential Revision: https://reviews.llvm.org/D45441

llvm-svn: 330824
2018-04-25 13:33:19 +00:00
Benjamin Kramer 0d97c225cd Fix -Wswitch warning after r330790.
source/Symbol/ClangASTContext.cpp:391:13: error: enumeration value 'HIP' not handled in switch [-Werror,-Wswitch]
    switch (IK.getLanguage()) {

llvm-svn: 330823
2018-04-25 13:22:47 +00:00
Simon Pilgrim 7574ffd7bc [llvm-mca][X86] Updated fma3 tests after rL330820
llvm-svn: 330822
2018-04-25 13:19:04 +00:00
Yaxun Liu 48390a992f Fix failure in lit test kernel-call.cu due to name mangling
llvm-svn: 330821
2018-04-25 13:07:58 +00:00
Simon Pilgrim dbd1ae7ddd [X86] Split WriteFMA into XMM, Scalar and YMM/ZMM scheduler classes
This removes all the FMA InstRW overrides.

If we ever get PR36924, then we can remove many of these declarations from models.

llvm-svn: 330820
2018-04-25 13:07:58 +00:00
Roman Lebedev cfa9e58ccf [X86][AArch64][NFC] Finish adding 'bad' tests for masked merge unfolding with constants.
I have initially committed basic tests in, rL330771,
but then quickly discovered that there are a few more
interesting patterns.

llvm-svn: 330819
2018-04-25 12:48:23 +00:00
Alexander Timofeev b934728cd2 [AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)
llvm-svn: 330818
2018-04-25 12:32:46 +00:00
Gabor Buella f4bd34b026 Avoid a warning on pointer casting, NFC
Reviewers: philip.pfaffe	

Reviewed By: philip.pfaffe	

Differential Revision: https://reviews.llvm.org/D46012

llvm-svn: 330817
2018-04-25 12:15:34 +00:00
Andrea Di Biagio 534e1dab79 [llvm-mca] Add a new option category for views.
With this patch, options to add/tweak views are all grouped together in the
-help output.

The new "View Options" category looks like this:

```
  View Options:

    -dispatch-stats                 - Print dispatch statistics
    -instruction-info               - Print the instruction info view
    -instruction-tables             - Print instruction tables
    -register-file-stats            - Print register file statistics
    -resource-pressure              - Print the resource pressure view
    -retire-stats                   - Print retire control unit statistics
    -scheduler-stats                - Print scheduler statistics
    -timeline                       - Print the timeline view
    -timeline-max-cycles=<uint>     - Maximum number of cycles in the timeline view. Defaults to 80 cycles
    -timeline-max-iterations=<uint> - Maximum number of iterations to print in timeline view
```

llvm-svn: 330816
2018-04-25 11:33:14 +00:00
Greg Bedwell 03e85e126c [UpdateTestChecks] Change update_mca_test_checks.py file mode to match the other scripts
llvm-svn: 330815
2018-04-25 11:20:42 +00:00
George Rimar d30a78b3fe [ELF] - Eliminate the AssertCommand.
Currently, LLD supports ASSERT as a separate command.

We support two forms now.

Assign expression-form: . = ASSERT(0x100)
(old GNU ld required it and some scripts in the wild are still using
something like . = ASSERT((_end - _text <= (512 * 1024 * 1024)), "kernel image bigger than KERNEL_IMAGE_SIZE");

Nowadays above is not a mandatory form and command-like form is commonly used:
ASSERT(<expr>, "text);

The return value of the ASSERT is Dot. That was implemented in D30171.
It looks like (2) is just a short version of (1) then.

GNU ld does *not* list ASSERT as a SECTIONS command:
https://sourceware.org/binutils/docs/ld/SECTIONS.html#SECTIONS

Given above we probably can change ASSERT to be an assignment to Dot. 
That makes the rest of the code much simpler. Patch do that.

Differential revision: https://reviews.llvm.org/D45434

llvm-svn: 330814
2018-04-25 11:16:31 +00:00
Simon Pilgrim 6a82e96ed9 [X86][SKX] Setup WriteFAdd and remove unnecessary InstRW scheduler overrides.
llvm-svn: 330813
2018-04-25 10:51:19 +00:00
Simon Pilgrim 98e21c5ade [X86][SNB] Remove unnecessary WriteFBlendLd InstRW scheduler overrides.
llvm-svn: 330812
2018-04-25 10:50:39 +00:00
Andrea Di Biagio 641cca3ddf [llvm-mca] run clang-format on a bunch of files. NFC
llvm-svn: 330811
2018-04-25 10:27:30 +00:00
Simon Dardis eac9301cdb [mips] Fix the definition of sync, synci
Also, fix the disassembly of synci for microMIPS.

Reviewers: abeserminji, smaksimovic, atanasyan

Differential Revision: https://reviews.llvm.org/D45870

llvm-svn: 330810
2018-04-25 10:19:22 +00:00
Andrea Di Biagio 93c49d5e58 [llvm-mca] Default to the native host cpu if flag -mcpu is not specified.
llvm-svn: 330809
2018-04-25 10:18:25 +00:00
Paul Semel 80daae2736 add check for long double for __builtin_dump_struct
llvm-svn: 330808
2018-04-25 10:09:20 +00:00
Andrea Di Biagio db66efcb6a [llvm-mca] Remove method Instruction::isZeroLatency(). NFCI
llvm-svn: 330807
2018-04-25 09:38:58 +00:00
Florian Hahn 1da30c659d [LoopInterchange] Use getExitBlock()/getExitingBlock instead of manual impl.
This also means we have to check if the latch is the exiting block now,
as `transform` expects the latches to be the exiting blocks too.

https://bugs.llvm.org/show_bug.cgi?id=36586

Reviewers: efriedma, davide, karthikthecool

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D45279

llvm-svn: 330806
2018-04-25 09:35:54 +00:00
Sander de Smalen eb896b148b [AArch64][SVE] Asm: Add AsmOperand classes for SVE gather/scatter addressing modes.
This patch adds parsing support for 'vector + shift/extend' and
corresponding asm operand classes, needed for implementing SVE's
gather/scatter addressing modes.

The added combinations of vector (ZPR) and Shift/Extend are:

Unscaled:
  ZPR64ExtLSL8:           signed 64-bit offsets  (z0.d)
  ZPR32ExtUXTW8:        unsigned 32-bit offsets  (z0.s, uxtw)
  ZPR32ExtSXTW8:          signed 32-bit offsets  (z0.s, sxtw)

Unpacked and unscaled:
  ZPR64ExtUXTW8:        unsigned 32-bit offsets  (z0.d, uxtw)
  ZPR64ExtSXTW8:          signed 32-bit offsets  (z0.d, sxtw)

Unpacked and scaled:
  ZPR64ExtUXTW<scale>:  unsigned 32-bit offsets  (z0.d, uxtw #<shift>)
  ZPR64ExtSXTW<scale>:    signed 32-bit offsets  (z0.d, sxtw #<shift>)

Scaled:
  ZPR32ExtUXTW<scale>:  unsigned 32-bit offsets  (z0.s, uxtw #<shift>)
  ZPR32ExtSXTW<scale>:    signed 32-bit offsets  (z0.s, sxtw #<shift>)
  ZPR64ExtLSL<scale>:   unsigned 64-bit offsets  (z0.d,  lsl #<shift>)
  ZPR64ExtLSL<scale>:     signed 64-bit offsets  (z0.d,  lsl #<shift>)


Patch [1/3] in series to add support for SVE's gather load instructions
that use scalar+vector addressing modes:
- Patch [1/3]: https://reviews.llvm.org/D45951
- Patch [2/3]: https://reviews.llvm.org/D46023
- Patch [3/3]: https://reviews.llvm.org/D45958

Reviewers: fhahn, rengolin, samparker, SjoerdMeijer, t.p.northover, echristo, evandro, javed.absar

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D45951

llvm-svn: 330805
2018-04-25 09:26:47 +00:00
Bjorn Pettersson bec2a7c4eb [DebugInfo] Invalidate debug info in ReassociatePass::RewriteExprTree
Summary:
When Reassociate is rewriting an expression tree it may
reuse old binary expression nodes, for new expressions.
Whenever an expression node is reused, but with a non-trivial
change in the result, we need to invalidate any debug info
that is associated with the node.

If for example rewriting
  x = mul a, b
  y = mul c, x
into
  x = mul c, b
  y = mul a, x
we still get the same result for 'y', but 'x' is a new expression.
All debug info referring to 'x' must be invalidated (marked as
optimized out) since we no longer calculate the expected value.

As a side-effect this patch avoid (at least some) problems where
reassociate could end up creating IR with debug-use before def.
Earlier the dbg.value nodes where left untouched in the IR, while
the reused binary nodes where sinked to just before the root node
of the rewritten expression tree. See PR27273 for more info about
such problems.

Reviewers: dblaikie, aprantl, dexonsmith

Reviewed By: aprantl

Subscribers: JDevlieghere, llvm-commits

Tags: #debug-info

Differential Revision: https://reviews.llvm.org/D45975

llvm-svn: 330804
2018-04-25 09:23:56 +00:00
Eric Liu 7920d2ea4e [clangd] Minor fixes for C++ standard library header mapping.
llvm-svn: 330803
2018-04-25 09:17:05 +00:00
Bjorn Pettersson 3dd22c9898 Fix buildbot problems after rC330794
Avoiding
  error: no matching function for call to 'makeArrayRef'
at
  ../tools/clang/lib/Parse/ParseTemplate.cpp:373:17

By using a local C array as input to makeArrayRef.

Not sure if this is the best solution, but it makes the code
compile again.

llvm-svn: 330802
2018-04-25 09:04:12 +00:00
Craig Topper 773ead2908 [TableGen] Fix bad indentation in tablegen output file.
llvm-svn: 330801
2018-04-25 06:24:51 +00:00
Tobias Grosser 5fa86378aa Update isl to isl-0.19-114-g385262af
llvm-svn: 330800
2018-04-25 06:10:35 +00:00
David Bolvansky 3ea50f9fef Merging r46043:
------------------------------------------------------------------------

llvm-svn: 330799
2018-04-25 04:33:36 +00:00
Faisal Vali 764216e1f9 [NFC] Make dependent parameter non-deducible, so that we are forced to use the default template parameter.
This might provide users with more graceful diagnostics if they should ever try and call this function with non-ConceptDecls.

llvm-svn: 330798
2018-04-25 03:54:20 +00:00
Craig Topper bba52806b1 [X86] Auto-generate complete checks. NFC
llvm-svn: 330797
2018-04-25 03:40:45 +00:00
Faisal Vali 699f45887f Fix rC330794 - a parameter that should have been dependent was inadvertently not -
and compiled in MSVC - but not so for the other bots.

The fix was to make it dependent as intended.

llvm-svn: 330796
2018-04-25 03:28:23 +00:00
Yaxun Liu 997e64f8a6 Fix lit test kernel-call.cu failure on ps4 due to dso_local
llvm-svn: 330795
2018-04-25 03:16:07 +00:00
Faisal Vali 936de9d666 [c++2a] [concepts] Add rudimentary parsing support for template concept declarations
This patch is a tweak of changyu's patch: https://reviews.llvm.org/D40381. It differs in that the recognition of the 'concept' token is moved into the machinery that recognizes declaration-specifiers - this allows us to leverage the attribute handling machinery more seamlessly.

See the test file to get a sense of the basic parsing that this patch supports. 

There is much more work to be done before concepts are usable...

Thanks Changyu!

llvm-svn: 330794
2018-04-25 02:42:26 +00:00
Yaxun Liu e21278d938 Fix failure in lit test kernel-call.cu
There is signext on ppc64. Just remove check for function argument.

llvm-svn: 330793
2018-04-25 02:34:04 +00:00
Geoff Berry 2af5f3c1e5 [DivRemPairs] Fix non-determinism in use list order.
Summary:
Use a MapVector instead of a DenseMap for RemMap since it is iteratated
over and the order of iteration can effect the order that new
instructions are created.  This can in turn effect the use list order of
div/rem input values if multiple new instructions are created that share
any input values.

Reviewers: spatel

Subscribers: mcrosier, llvm-commits

Differential Revision: https://reviews.llvm.org/D45858

llvm-svn: 330792
2018-04-25 02:17:56 +00:00
Billy Robert O'Neal III 078611eed5 [libcxx] [test] Remove nonportable that errc::is_a_directory produces "Is a directory" from ios_base::failure tests
These io_error asserts that std::errc::is_a_directory has message "Is a directory". On MSVC++ it reports "is a directory" (with a lowercase I). That doesn't matter for the ios_failure component being tested, so just implement in terms of system_category().message().

Reviewed as https://reviews.llvm.org/D45715

llvm-svn: 330791
2018-04-25 01:58:55 +00:00
Yaxun Liu 887c569bcb [HIP] Add hip input kind and codegen for kernel launching
HIP is a language similar to CUDA (https://github.com/ROCm-Developer-Tools/HIP/blob/master/docs/markdown/hip_kernel_language.md ).
The language syntax is very similar, which allows a hip program to be compiled as a CUDA program by Clang. The main difference
is the host API. HIP has a set of vendor neutral host API which can be implemented on different platforms. Currently there is open source
implementation of HIP runtime on amdgpu target (https://github.com/ROCm-Developer-Tools/HIP).

This patch adds support of input kind and language standard hip.

When hip file is compiled, both LangOpts.CUDA and LangOpts.HIP is turned on. This allows compilation of hip program as CUDA
in most cases and only special handling of hip program is needed LangOpts.HIP is checked.

This patch also adds support of kernel launching of HIP program using HIP host API.

When -x hip is not specified, there is no behaviour change for CUDA.

Patch by Greg Rodgers.
Revised and lit test added by Yaxun Liu.

Differential Revision: https://reviews.llvm.org/D44984

llvm-svn: 330790
2018-04-25 01:10:37 +00:00
Richard Trieu 7282d320b7 [ODRHash] Hash template arguments of methods.
llvm-svn: 330789
2018-04-25 00:31:15 +00:00
Rafael Espindola 61376d9bed Bring r329960 back.
The fix is to copy Used when replacing the symbol.

Original message:

Do not keep shared symbols created from garbage-collected eliminated DSOs.

If all references to a DSO happen to be weak, and if the DSO is
specified with --as-needed, the DSO is not added to DT_NEEDED.
If that happens, we also need to eliminate shared symbols created
from the DSO. Otherwise, they become dangling references that point
to non-exsitent DSO.

Fixes https://bugs.llvm.org/show_bug.cgi?id=36991

Differential Revision: https://reviews.llvm.org/D45536

llvm-svn: 330788
2018-04-25 00:29:13 +00:00
Chandler Carruth 69e68f8468 [PM/LoopUnswitch] Begin teaching SimpleLoopUnswitch to use the new
update API for dominators rather than doing manual, hacky updates.

This is just the first step, but in some ways the most important as it
moves the non-trivial unswitching to update the domtree rather than
fully recalculating it each time.

Subsequent patches should remove the custom update logic used by the
trivial unswitch and replace it with uses of the update API.

This also fixes a number of bugs I was seeing when testing non-trivial
unswitch due to it querying the quasi-correct dominator tree. Now the
tree is 100% correct and safe to query. That said, there are still more
bugs I can see with non-trivial unswitch just running over the test
suite, so more bugfix patches are needed as well.

Thanks to both Sanjoy and Fedor for reviews and testing!

Differential Revision: https://reviews.llvm.org/D45943

llvm-svn: 330787
2018-04-25 00:18:07 +00:00
Bob Haarman 8832f88996 [COFF] create MemoryBuffers without requiring NUL terminators
Summary:
In a number of places in the COFF linker, we were calling
MemoryBuffer::getFile() with default parameters. This causes LLVM to
NUL-terminate the buffers, which can prevent them from being memory
mapped. Since we operate on binary and do not use NUL as an indicator
of the end of the file content, this change causes us to not require
the NUL terminator anymore.

Reviewers: ruiu, pcc

Reviewed By: ruiu

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45909

llvm-svn: 330786
2018-04-24 23:16:39 +00:00
Rui Ueyama ffa650a183 Style fix.
llvm-svn: 330785
2018-04-24 23:09:57 +00:00
Rafael Espindola a8d0b87f50 Add a test. NFC.
This would have found the issue in r329960.

llvm-svn: 330784
2018-04-24 23:03:58 +00:00
Jessica Paquette 4f56428de1 [MachineOutliner] Check for explicit uses of LR/W30 in MI operands
Before, the outliner would grab ADRPs that used LR/W30. This patch fixes
that by checking for explicit uses of those registers before the special-casing
for ADRPs.

This also adds a test that ensures that those sorts of ADRPs won't be outlined.

llvm-svn: 330783
2018-04-24 22:38:15 +00:00
Craig Topper f3cefad255 [DAGCombiner][X86] When promoting loads don't use ZEXTLOAD even its legal
We were previously prefering ZEXTLOAD over EXTLOAD if it is legal. This triggers during X86's promotion of i16->i32. Not sure about other targets.

Using ZEXTLOAD can prevent folding it to SEXTLOAD later if we were to promote a sign extended operand like we would need for SRA. However, X86 doesn't currently promote i16 SRA. I was looking into doing that which is how I found this issue.

This is also blocking our ability to fold 4 byte aligned EXTLOADs with "loadi32". This is what caused most of the test changes here.

Differential Revision: https://reviews.llvm.org/D45585#inline-402825

llvm-svn: 330781
2018-04-24 22:35:27 +00:00
Dan Albert 07b0059083 Revert "[Driver] Android triples are not aliases for other triples."
Revering while I diagnose the failures.

This reverts commit 82dc3bf2157da280420f80e654292cb05e0dc5f7.

llvm-svn: 330780
2018-04-24 22:06:40 +00:00