Commit Graph

950 Commits

Author SHA1 Message Date
Matt Arsenault cf9a9a148e R600: Report that integer division is expensive.
Divides by weird constants now emit much better code.

llvm-svn: 210995
2014-06-15 19:48:16 +00:00
Matt Arsenault 66ee0816da R600: Remove dead code
llvm-svn: 210994
2014-06-15 19:48:13 +00:00
Matt Arsenault b2e8744eeb Fix typo
llvm-svn: 210968
2014-06-14 04:26:07 +00:00
Matt Arsenault e682a19a1c R600: Fix asserts related to constant initializers
This would assert if a constant address space was extern
and therefore didn't have an initializer. If the initializer
was undef, it would hit the unreachable unhandled initializer case.

An extern global should never really occur since we don't have
machine linking, but bugpoint likes to remove initializers.

llvm-svn: 210967
2014-06-14 04:26:05 +00:00
Matt Arsenault 41aa27c96b R600: Use address space enum instead of value
llvm-svn: 210966
2014-06-14 04:26:01 +00:00
Matt Arsenault fd8c24ede8 R600: Cleanup some old AMDIL stuff.
Move / delete some of the more obviously wrong
setOperationAction calls. Most of these are setting Expand
for types that aren't legal which is the default anyway.
Leave stuff that might require more thought on whether it's
junk or not as it is.

No functionality change.

llvm-svn: 210922
2014-06-13 17:20:53 +00:00
Tom Stellard bc5b5370de R600: Remove AMDIL instruction and register definitions
Most of these are no longer used any more.

llvm-svn: 210915
2014-06-13 16:38:59 +00:00
Matt Arsenault c02eea7f64 R600: Don't call setOperationAction with things that aren't opcodes.
CondCode actions are set with setCondCodeAction.
This should have been a harmless bug since the values seem to only
collide only with nodes that don't need to be handled, and these are
already correctly setup elsewhere.

llvm-svn: 210888
2014-06-13 07:44:38 +00:00
Matt Arsenault 825fb0b094 R600/SI: Fix selection error on i64 rotl / rotr.
Evergreen is still broken due to missing shl_parts.

llvm-svn: 210885
2014-06-13 04:00:30 +00:00
Tom Stellard 2e59a45f80 R600: Move AMDGPUInstrInfo from AMDGPUTargetMachine into AMDGPUSubtarget
llvm-svn: 210869
2014-06-13 01:32:00 +00:00
Tom Stellard d881e9195a R600: Drop use of cached TargetMachine in R600InstrInfo.cpp
llvm-svn: 210868
2014-06-13 01:31:56 +00:00
Tom Stellard bfd480d79f R600: Drop use of cached TargetMachine in AMDGPUInstrInfo.cpp
llvm-svn: 210865
2014-06-13 01:02:57 +00:00
Matt Arsenault 5d47d4ac7e R600: Mostly remove remaining AMDIL intrinsics.
Delete all unused ones, and add new AMDGPU named intrinsics for
the ones that are. Handle the old AMDIL names for comptability (although
remove their GCCBuiltin names) and add tests since there weren't any
for these before.

llvm-svn: 210827
2014-06-12 21:15:44 +00:00
Matt Arsenault 2c81994f92 R600/SI: Use a register set to -1 for data0 on ds_inc*/ds_dec*
There is not such thing as a 0-data ds instruction, and the data
operand needs to be a vgpr set to something meaningful.

llvm-svn: 210756
2014-06-12 08:21:54 +00:00
Tom Stellard 4a9cea608c R600: Set correct InstrItinClass for instructions using *Helper classes
We weren't doing this before, so all instruction using the *Helper
classes were considered for any ALU slot.

This fixes a hang in the builtin-char-clz-1.0.generated.cl piglit test.

llvm-svn: 210703
2014-06-11 20:51:42 +00:00
Tom Stellard 3fe21f8afa R600: BCNT_INT is a vector only instruction
llvm-svn: 210702
2014-06-11 20:51:39 +00:00
Matt Arsenault 2acc7a4570 R600/SI: Fix bitcast between v2i32 and f64
This is the same problem fixed in r210664 for more types.

The test passes without this fix. For some reason
I'm only hitting this when creating selects lowered
to v2i32 selects.

llvm-svn: 210692
2014-06-11 19:31:13 +00:00
Matt Arsenault 845438204f R600/SI: Update place using old subtarget predicate
llvm-svn: 210683
2014-06-11 18:11:34 +00:00
Matt Arsenault caa0ec2851 R600/SI: Add common 64-bit LDS atomics
llvm-svn: 210680
2014-06-11 18:08:54 +00:00
Matt Arsenault 1f10c5e2c9 R600/SI: Add instruction definitions for 64-bit LDS atomics
llvm-svn: 210679
2014-06-11 18:08:50 +00:00
Matt Arsenault c793e1d9dc R600/SI: Add 32-bit LDS atomic cmpxchg
llvm-svn: 210678
2014-06-11 18:08:48 +00:00
Matt Arsenault 9e874541ac R600/SI: Use LDS atomic inc / dec
llvm-svn: 210677
2014-06-11 18:08:45 +00:00
Matt Arsenault 0e69e8128c R600/SI: Add other LDS atomic operations
llvm-svn: 210676
2014-06-11 18:08:42 +00:00
Matt Arsenault 8c6613d2bf R600/SI: Add instruction definitions for more LDS ops
llvm-svn: 210675
2014-06-11 18:08:39 +00:00
Matt Arsenault 7ddcd83d49 R600/SI: Fix backwards names for local atomic instructions.
The manual lists them as *_RTN_U32, not *_U32_RTN, which is more
consistent with how every other sized instruction is named.

llvm-svn: 210674
2014-06-11 18:08:37 +00:00
Matt Arsenault 725741004c R600/SI: Refactor local atomics.
Use patterns that will also match the immediate offset to
match the normal read / writes.

llvm-svn: 210673
2014-06-11 18:08:34 +00:00
Matt Arsenault 364a6747aa R600/SI: Use v_cvt_f32_ubyte* instructions
This eliminates extra extract instructions when loading an i8 vector to
a float vector.

llvm-svn: 210666
2014-06-11 17:50:44 +00:00
Matt Arsenault 064c206d23 R600/SI: Fix selection failure on scalar_to_vector
There seem to be only 2 places that produce these,
and it's kind of tricky to hit them.

Also fixes failure to bitcast between i64 and v2f32,
although this for some reason wasn't actually broken in the
simple bitcast testcase, but did in the scalar_to_vector one.

llvm-svn: 210664
2014-06-11 17:40:32 +00:00
Rafael Espindola ace0080a4a Try to fix the msvc build.
llvm-svn: 210636
2014-06-11 04:41:37 +00:00
Matt Arsenault 10da3b2516 Use cast instead of assert + dyn_cast
llvm-svn: 210628
2014-06-11 03:30:06 +00:00
Matt Arsenault c9df794042 R600: Add helper functions.
Extract these from some of my other patches, since this
is the only thing really making them dependent on each other.

llvm-svn: 210627
2014-06-11 03:29:54 +00:00
Tom Stellard 4e07b1d76b R600/SI: Emit an error when attempting to spill VGPRs v4
I can't get VGPR spilling to work reliable, so for now just emit
an error when the register allocator tries to spill VGPRs.

v2:
  - Fix build
v3:
  - Added crash fix when spilling SPGRs
v4:
  - Use V_MOV_B32 as a dummy instruction instead of S_NOP

Patch by: Darren Powell

https://bugs.freedesktop.org/show_bug.cgi?id=75276

llvm-svn: 210588
2014-06-10 21:20:41 +00:00
Tom Stellard 060ae39022 R600/SI: Fix a crash when spilling SGPRs
We need to make sure only one new instruction is added when spilling
otherwise the register allocator may crash.

This fixes a crash in the game Antichamber.

https://bugs.freedesktop.org/show_bug.cgi?id=75276

llvm-svn: 210587
2014-06-10 21:20:38 +00:00
Matt Arsenault 6042506b5c R600: Use BCNT_INT for evergreen
llvm-svn: 210569
2014-06-10 19:18:28 +00:00
Matt Arsenault 8333e4378e R600/SI: Implement i64 ctpop
llvm-svn: 210568
2014-06-10 19:18:24 +00:00
Matt Arsenault b5b5110b5c R600/SI: Use bcnt instruction for ctpop
llvm-svn: 210567
2014-06-10 19:18:21 +00:00
Matt Arsenault 6e43965fbc R600: Handle fcopysign
llvm-svn: 210564
2014-06-10 19:00:20 +00:00
Matt Arsenault b2cbf799d1 R600/SI: Handle sign_extend and zero_extend to i64 with patterns.
llvm-svn: 210563
2014-06-10 18:54:59 +00:00
Tom Stellard 3ca1bfc728 SelectionDAG: Expand SELECT_CC to SELECT + SETCC
This consolidates code from the Hexagon, R600, and XCore targets.

No functionality change intended.

llvm-svn: 210539
2014-06-10 16:01:22 +00:00
Matt Arsenault 93840c095a R600/SI: Rename VOP3 helper class to be more general
It has other uses besides shift instructions.

llvm-svn: 210478
2014-06-09 17:00:46 +00:00
Matt Arsenault 689f325099 R600/SI: Keep 64-bit not on SALU
llvm-svn: 210476
2014-06-09 16:36:31 +00:00
Matt Arsenault 13ccc8f1bc R600: Fix selection failure for vector bswap
llvm-svn: 210475
2014-06-09 16:20:25 +00:00
Matt Arsenault 151304691c R600/SI: Match rsq instructions
llvm-svn: 210226
2014-06-05 00:15:55 +00:00
Matt Arsenault c6f338dd5e Use nullptr
llvm-svn: 210222
2014-06-05 00:01:12 +00:00
Matt Arsenault 08d84943af Fix typos
llvm-svn: 210135
2014-06-03 23:06:13 +00:00
Matt Arsenault 616a8e42b1 R600: Set all float vector expands in the same place
llvm-svn: 209988
2014-06-01 07:38:21 +00:00
Matt Arsenault b9e1eec363 R600/SI: Remove redundant patterns
These patterns are already handled in the instruction definition.

llvm-svn: 209979
2014-05-31 19:25:17 +00:00
Matt Arsenault aeca2fa9f7 R600/SI: Fix [s|u]int_to_fp for i1
llvm-svn: 209971
2014-05-31 06:47:42 +00:00
Matt Arsenault b5c4835502 R600/SI: Fix pattern variable names.
These are confusing enough since the order swaps,
so give them more useful names.

llvm-svn: 209787
2014-05-29 01:18:01 +00:00
Matt Arsenault 46b51b7f62 R600: Add definition for flat address space ID.
Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.

llvm-svn: 209463
2014-05-22 18:27:07 +00:00