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943 Commits

Author SHA1 Message Date
Colin LeMahieu cefca69d72 [Hexagon] Adding vector shift instructions and tests. 
llvm-svn: 227619
 2015-01-30 21:58:46 +00:00
Colin LeMahieu cc4329b836 [Hexagon] Adding vector predicate instructions. 
llvm-svn: 227613
 2015-01-30 21:24:06 +00:00
Colin LeMahieu 26a537c743 [Hexagon] Adding vector permutation instructions and tests. 
llvm-svn: 227612
 2015-01-30 21:14:00 +00:00
Colin LeMahieu 16f5e56703 [Hexagon] Adding vector multiplies. Cleaning up tests. 
llvm-svn: 227609
 2015-01-30 20:56:54 +00:00
Colin LeMahieu b84ec02296 [Hexagon] Adding XTYPE/COMPLEX instructions and cleaning up tests. 
llvm-svn: 227607
 2015-01-30 20:08:37 +00:00
Colin LeMahieu 21fbc94777 [Hexagon] Adding XTYPE/ALU vector instructions. Organizing test files. 
llvm-svn: 227598
 2015-01-30 19:13:26 +00:00
Colin LeMahieu 709c0a16bb [Hexagon] Adding a number of vector load variants and organizing tests. 
llvm-svn: 227588
 2015-01-30 18:09:44 +00:00
Colin LeMahieu 3c740a3614 [Hexagon] Organizing tests and adding a few missing jump instruction encodings. 
llvm-svn: 227498
 2015-01-29 21:47:15 +00:00
Colin LeMahieu bc63f42e0d [Hexagon] Adding missing instruction encodings and tests. 
llvm-svn: 227495
 2015-01-29 21:30:22 +00:00
Colin LeMahieu bd4770f915 [Hexagon] Adding alu vector instructions 
llvm-svn: 227493
 2015-01-29 21:09:30 +00:00
Vladimir Medic df464ae224 [Mips][Disassembler] When disassembler meets cache/pref instructions for r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method for R6 CACHE_HINT_DESC class that properly handles decoding of these instructions. 
llvm-svn: 227430
 2015-01-29 11:33:41 +00:00
Colin LeMahieu 1de7e0d923 [Hexagon] Updating many V4 intrinsic patterns. Adding missing instruction and deleting unused classes. 
llvm-svn: 227353
 2015-01-28 19:39:09 +00:00
Colin LeMahieu 94c33218e3 [Hexagon] Adding XTYPE/MPY intrinsic tests and some missing multiply instructions. 
llvm-svn: 227347
 2015-01-28 19:16:17 +00:00
Colin LeMahieu fe03c9a678 [Hexagon] Replacing XTYPE/SHIFT intrinsic patternss. Adding tests and missing instructions with tests. 
llvm-svn: 227330
 2015-01-28 17:37:59 +00:00
Jozef Kolek e10a02ecf0 [mips][microMIPS] Implement LWGP instruction 
Differential Revision: http://reviews.llvm.org/D6650

llvm-svn: 227325
 2015-01-28 17:27:26 +00:00
Craig Topper 7d3c6d307a [X86] Teach disassembler to handle illegal immediates on AVX512 integer compare instructions. 
llvm-svn: 227302
 2015-01-28 10:09:56 +00:00
Vladimir Medic 0516a5b686 When disassembler meets compact jump instructions for r6 it crashes as the access to operands array is out of range. This patch removes dedicated decoder method that wrongly handles decoding of these instructions. 
llvm-svn: 227084
 2015-01-26 10:33:43 +00:00
Reid Kleckner f4ebbc6825 mips: Fix "XPASS" test results by removing 'not' commands 
These tests are asserting and crashing for me, and 'not' sees that as a
non-zero exit code instead of a signal code for obscure Windows reasons.
This causes the test to pass, giving me an unclean 'ninja check'.

The test is already XFAILd, so just run the test without 'not' and let
lit handle the failure.

llvm-svn: 226958
 2015-01-23 22:55:31 +00:00
Jozef Kolek 5cfebdde2b [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B 
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514

llvm-svn: 226657
 2015-01-21 12:39:30 +00:00
Jozef Kolek 2c6d73207e [mips][microMIPS] Implement ADDIUPC instruction 
Differential Revision: http://reviews.llvm.org/D6582

llvm-svn: 226656
 2015-01-21 12:10:11 +00:00
Vladimir Medic 435cf8a415 [Mips][Disassembler]When disassembler meets load/store from coprocessor 2 instructions for mips r6 it crashes as the access to operands array is out of range. This patch adds dedicated decoder method that properly handles decoding of these instructions. 
llvm-svn: 226652
 2015-01-21 10:47:36 +00:00
Craig Topper 620b50cc23 [X86] Convert all the i8imm used by SSE and AVX instructions to u8imm. 
This makes the assembler check their size and removes a hack from the disassembler to avoid sign extending the immediate.

llvm-svn: 226645
 2015-01-21 08:15:54 +00:00
Jozef Kolek 0d49117769 Reverted revision 226577. 
llvm-svn: 226595
 2015-01-20 19:29:28 +00:00
Jozef Kolek 45f7f9c1ab [mips][microMIPS] MicroMIPS 16-bit unconditional branch instruction B 
Implement microMIPS 16-bit unconditional branch instruction B.

Implemented 16-bit microMIPS unconditional instruction has real name B16, and
B is an alias which expands to either B16 or BEQ according to the rules:
b 256 --> b16 256 # R_MICROMIPS_PC10_S1
b 12256 --> beq $zero, $zero, 12256 # R_MICROMIPS_PC16_S1
b label --> beq $zero, $zero, label # R_MICROMIPS_PC16_S1

Differential Revision: http://reviews.llvm.org/D3514

llvm-svn: 226577
 2015-01-20 16:45:27 +00:00
Daniel Sanders 01dce6c931 [mips] 'CHECK :' is not a valid check directive. Fixed. 
llvm-svn: 226409
 2015-01-18 18:43:10 +00:00
Daniel Sanders 0cb9dc6e68 [mips] Make whitespace in disassembler tests more consistent. NFC. 
The tests for the ISA's should now be approximately diffable. That is, the
output of 'diff valid-mips1.txt valid-mips2.txt' should be emit the lines
for instructions that were added/removed to/from MIPS-I by MIPS-II. This
doesn't work perfectly at the moment due to ordering differences but it
should be close.

llvm-svn: 226408
 2015-01-18 18:38:36 +00:00
Daniel Sanders 46ad7cbfce [mips] Make whitespace of disassembler tests more consistent by removing blank lines. NFC. 
llvm-svn: 226407
 2015-01-18 18:21:19 +00:00
Colin LeMahieu cd9c4e3e07 [Hexagon] Adding new-value store and bit reverse instructions. 
llvm-svn: 226224
 2015-01-15 23:10:29 +00:00
Colin LeMahieu 538b85810c [Hexagon] Removing old versions of vsplice, valign, cl0, ct0 and updating references to new versions. 
llvm-svn: 226194
 2015-01-15 19:28:32 +00:00
Colin LeMahieu 504157f1ae [Hexagon] Adding vmux instruction. Removing old transfer instructions and updating references. 
llvm-svn: 226184
 2015-01-15 18:16:00 +00:00
Vladimir Medic df3ed1c9d6 Add disassembler tests for mips64r6 platform. There are no functional changes. 
llvm-svn: 226166
 2015-01-15 14:18:12 +00:00
Vladimir Medic d6d486ddcc Add disassembler tests for mips32r6 platform. There are no functional changes. 
llvm-svn: 226165
 2015-01-15 14:11:38 +00:00
Vladimir Medic 5dcf17b881 Add disassembler tests for mips64r2 platform. There are no functional changes. 
llvm-svn: 226164
 2015-01-15 14:06:34 +00:00
Vladimir Medic e993dac523 Add disassembler tests for mips64 platform. There are no functional changes. 
llvm-svn: 226151
 2015-01-15 08:50:20 +00:00
Hal Finkel 64202167c5 [PowerPC] Add assembler support for mcrfs and friends 
Fill out our support for the floating-point status and control register
instructions (mcrfs and friends). As it turns out, these are necessary for
compiling src/test/harness_fp.h in TBB for PowerPC.

Thanks to Raf Schietekat for reporting the issue!

llvm-svn: 226070
 2015-01-15 01:00:53 +00:00
Vladimir Medic 1080666e80 Add disassembler tests for mips32r2 platform. There are no functional changes. 
llvm-svn: 225980
 2015-01-14 11:35:22 +00:00
Vladimir Medic 62dfce3240 Add disassembler tests for mips32r2 platform. There are no functional changes. 
llvm-svn: 225967
 2015-01-14 10:18:56 +00:00
Jozef Kolek 9761e96b01 [mips][microMIPS] Implement BEQZ16 and BNEZ16 instructions 
Differential Revision: http://reviews.llvm.org/D5271

llvm-svn: 225627
 2015-01-12 12:03:34 +00:00
Craig Topper 7c10252943 [X86] Don't print 'dword ptr' or 'qword ptr' on the operand to some of the LEA variants in Intel syntax. The memory operand is inherently unsized. 
llvm-svn: 225432
 2015-01-08 07:41:30 +00:00
Colin LeMahieu 627df427eb [Hexagon] Adding floating point classification and creation. 
llvm-svn: 225374
 2015-01-07 20:28:57 +00:00
Colin LeMahieu 290ece7d4c [Hexagon] Adding encodings for v5 floating point instructions. 
llvm-svn: 225372
 2015-01-07 20:24:09 +00:00
Colin LeMahieu 777abcb1d7 [Hexagon] Adding encoding for popcount, fastcorner, dword asr with rounding. 
llvm-svn: 225371
 2015-01-07 20:07:28 +00:00
Colin LeMahieu 507dd32703 [Hexagon] Adding compound jump encodings. 
llvm-svn: 225291
 2015-01-06 20:03:31 +00:00
Colin LeMahieu 68b2e050f0 [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, dcfetch. 
llvm-svn: 225283
 2015-01-06 19:03:20 +00:00
Colin LeMahieu d9c605ddae [Hexagon] Adding encoding information for absolute address loads. 
llvm-svn: 225279
 2015-01-06 18:38:26 +00:00
Colin LeMahieu 1445553474 [Hexagon] Adding dealloc_return encoding and absolute address stores. 
llvm-svn: 225267
 2015-01-06 16:15:15 +00:00
Craig Topper 639445494f [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16. 
Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building.

llvm-svn: 225256
 2015-01-06 08:59:30 +00:00
Colin LeMahieu dacf057bdc [Hexagon] Adding add/sub with carry, logical shift left by immediate and memop instructions. Removing old defs without bits and updating references. 
llvm-svn: 225210
 2015-01-05 21:36:38 +00:00
Colin LeMahieu 28bb02a8c7 [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and accumulating shifts. 
llvm-svn: 225201
 2015-01-05 20:56:41 +00:00
Colin LeMahieu abdf2b37d8 [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without encoding bits. 
llvm-svn: 225199
 2015-01-05 20:35:54 +00:00