793c592652
[AMDGPU][MC] New syntax for ds_swizzle_b32 offset
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See Bug 28601: https://bugs.llvm.org//show_bug.cgi?id=28601
Reviewers: artem.tamazov, vpykhtin
Differential Revision: https://reviews.llvm.org/D33542
llvm-svn: 304309
2017-05-31 16:26:47 +00:00
2fb5960121
Revert earlier change. ds permute operations affect lgkm counter.
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Differential Revision: https://reviews.llvm.org/D32254
llvm-svn: 300791
2017-04-19 23:39:19 +00:00
e6ef099dcd
[AMDGPU][MC] Corrected ds_write_src2_* to require one offset instead of two.
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Fixed bug 32551: https://bugs.llvm.org//show_bug.cgi?id=32551
Reviewers: vpykhtin
Differential Revision: https://reviews.llvm.org/D31809
llvm-svn: 300319
2017-04-14 12:28:07 +00:00
7184c44d66
[AMDGPU][MC] Corrected ds_wrxchg2* to support two offsets
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Fixed bug 28227: https://bugs.llvm.org//show_bug.cgi?id=28227
Reviewers: vpykhtin
Differential Revision: https://reviews.llvm.org/D31808
llvm-svn: 300066
2017-04-12 14:29:45 +00:00
acb089e12a
[AMDGPU] Add a new pass to insert waitcnts. Leave under an option for testing.
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Based on comments in https://reviews.llvm.org/D31161 .
llvm-svn: 300023
2017-04-12 03:25:12 +00:00
e5147247b8
[AMDGPU][MC] Fix for Bug 28211 + LIT tests
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- corrected DS_GWS_* opcodes (see VI_Shader_Programming#16.pdf for detailed description)
- address operand is not used
- several opcodes have data operand
- all opcodes have offset modifier
- DS_AND_SRC2_B32: corrected typo in mnemo
- DS_WRAP_RTN_F32 replaced with DS_WRAP_RTN_B32
- added CI/VI opcodes:
- DS_CONDXCHG32_RTN_B64
- DS_GWS_SEMA_RELEASE_ALL
- added VI opcodes:
- DS_CONSUME
- DS_APPEND
- DS_ORDERED_COUNT
Differential Revision: https://reviews.llvm.org/D31707
llvm-svn: 299767
2017-04-07 13:07:13 +00:00
781249833b
AMDGPU: Add ds_nop to assembler
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llvm-svn: 296513
2017-02-28 20:15:46 +00:00
dedc544ac7
AMDGPU: Add definitions for ds_{read|write}_b{96|128}
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It's not clear to me if this is always better than
doing ds_write2_b64 This adds the constraint of
a 128-bit register input instead of a pair of
64-bit.
llvm-svn: 296512
2017-02-28 20:15:43 +00:00
43b61561b0
[AMDGPU][mc] Fix AddressSanitizer leftover issue in gfx7_asm_all test
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Issue occurs when assembling "ds_ordered_count v0, v0 gds".
llvm-svn: 294004
2017-02-03 12:47:30 +00:00
115a61560e
AMDGPU: Add VI i16 support
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Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 286464
2016-11-10 16:02:37 +00:00
2d2d33f1dc
Revert "AMDGPU: Add VI i16 support"
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This reverts commit r285939 and r285948. These broke some conformance tests.
llvm-svn: 285995
2016-11-04 13:06:34 +00:00
2b3379cdff
AMDGPU: Add VI i16 support
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Patch By: Wei Ding
Differential Revision: https://reviews.llvm.org/D18049
llvm-svn: 285939
2016-11-03 17:13:50 +00:00
f3dd863031
AMDGPU: Whitespace fixes
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llvm-svn: 285659
2016-11-01 00:55:14 +00:00
751985a757
[AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.
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Fixes Bug 28215. Lit tests updated.
Differential Revision: https://reviews.llvm.org/D25837
llvm-svn: 284825
2016-10-21 14:49:22 +00:00
10c17ca6c6
AMDGPU: Partially fix reported code size for some instructions
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These ones need to have the size on the pseudo instruction set for
getInstSizeInBytes to work correctly. These also have a statically
known size.
llvm-svn: 283437
2016-10-06 10:13:23 +00:00
2e217b87cb
[AMDGPU][mc] Add support for ds_add_[rtn_]f32.
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Lit tests added.
Resolves https://github.com/RadeonOpenCompute/hcc/issues/122 .
Differential Revision: https://reviews.llvm.org/D24765
llvm-svn: 282086
2016-09-21 16:35:44 +00:00
902db3101b
[AMDGPU] refactor DS instruction definitions. NFC.
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Differential revision: https://reviews.llvm.org/D22522
llvm-svn: 277344
2016-08-01 14:21:30 +00:00
Dmitry Preobrazhensky