Commit Graph

16 Commits

Author SHA1 Message Date
Chandler Carruth 2946cd7010 Update the file headers across all of the LLVM projects in the monorepo
to reflect the new license.

We understand that people may be surprised that we're moving the header
entirely to discuss the new license. We checked this carefully with the
Foundation's lawyer and we believe this is the correct approach.

Essentially, all code in the project is now made available by the LLVM
project under our new license, so you will see that the license headers
include that license only. Some of our contributors have contributed
code under our old license, and accordingly, we have retained a copy of
our old license notice in the top-level files in each project and
repository.

llvm-svn: 351636
2019-01-19 08:50:56 +00:00
Craig Topper 66572df76e [X86] Add NotMemoryFoldable to a bunch of instructions to suppress them from the autogenerated load folding table.
Most of these are system instructions or other instructions we don't use in CodeGen. No point wasting space for them in the table. Removing them from the autogenerated table makes it easier to review the manual table.

A few are real opcode collisions where the memory and register forms are completely different instructions.

llvm-svn: 334474
2018-06-12 04:34:59 +00:00
Craig Topper 860562c915 [X86] Miscellaneous fixes to get the load folding table generator to work again.
llvm-svn: 334377
2018-06-10 21:48:24 +00:00
Craig Topper 9e11f96df6 [X86] Remove mayLoad flag from BNDMK/BNDCL/BNDCN/BNDCU.
The instruction documentation specifically says that these instruction don't access memory.

llvm-svn: 331105
2018-04-28 06:58:27 +00:00
Craig Topper 6d6b2b9503 [X86] Change memory operand of BNDMK/BNDCL/BNDCU/BNDCN/BNDST to anymem.
These instruction don't use their memory operands as normal memory operands. They're just used as addresses. They don't have a size because they aren't directly representing a load or store.

llvm-svn: 331104
2018-04-28 06:58:26 +00:00
Craig Topper ef3866a859 [X86] Remove REX.W from 64-bit mode BND instructions.
As far as I can tell from the docs, the instructions are automatically 64-bit in 64-bit mode. We don't need REX.W.

llvm-svn: 331102
2018-04-28 06:02:40 +00:00
Craig Topper 8a6532ae84 [X86] Rename BNDMOV instructions and hide redundant instruction encoding from the assembler.
Favor the 0x1a encoding for register/register move to match gas.

The instructions used RM and MR in their name along with rr/rm/mr at the end. To make more consistent with other instructions remove the RM/MR and use rr/rm/mr/rr_REV.

Hide the _REV encoding from the assembler but leave it for the disassembler.

llvm-svn: 331101
2018-04-28 06:02:39 +00:00
Simon Pilgrim e0c7868ded Remove comment references to itineraries. NFCI.
llvm-svn: 330021
2018-04-13 14:31:57 +00:00
Simon Pilgrim 0cd0fbd8c5 [X86] Remove system/control schedule itineraries (PR37093)
llvm-svn: 329903
2018-04-12 12:09:24 +00:00
Craig Topper 914b1d524c [X86] Change BNDLDX to use anymem instead of i64mem for itsmemory operand.
This instruction doesn't access memory. It juse use a similar looking memory encoding. Don't require Intel syntax to put "qword ptr" in front of it.

llvm-svn: 320845
2017-12-15 19:01:50 +00:00
Simon Pilgrim 42fcda9a6c [X86][MPX] Tag MPX instructions scheduler classes
Currently tagged these as system instructions, once we have uses for them (ASAN?) and they are faster we will need to improve on this.

llvm-svn: 320173
2017-12-08 19:03:42 +00:00
Ayman Musa 62d1c71676 [X86] Added missing mayLoad/mayStore attributes to some X86 instructions.
Throughout the effort of automatically generating the X86 memory folding tables these missing information were encountered.
This is a preparation work for a future patch including the automation of these tables.

Differential Revision: https://reviews.llvm.org/D31714

llvm-svn: 300190
2017-04-13 10:03:45 +00:00
Craig Topper 955308fbee [X86] Remove many operands that represent memory stores from outs to ins. These operands are the registers and immediates that specify the memory address not the memory itself thus they are inputs.
llvm-svn: 263354
2016-03-13 02:56:31 +00:00
Craig Topper 5be407ab27 [X86] Remove extra spaces from MPX instruction asm strings.
llvm-svn: 257298
2016-01-11 00:44:46 +00:00
Craig Topper 1b94d9a3cc [X86] Use PS instead of TB for instructions that have PD/XS/XD variations. Use OpSize32 on an instruction that has an OpSize16 variant.
llvm-svn: 256918
2016-01-06 06:18:41 +00:00
Elena Demikhovsky 6b62b659cb X86-MPX: Implemented encoding for MPX instructions.
Added encoding tests.

llvm-svn: 239403
2015-06-09 13:02:10 +00:00