d8d1dcc09a
Use a more efficient lowering of uint64_t --> float that can take advantage of hardware signed integer conversion without
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having to do a double cast (uint64_t --> double --> float). This is based on the algorithm from compiler_rt's __floatundisf
for X86-64.
llvm-svn: 115634
2010-10-05 17:24:05 +00:00
7681b41720
test/CodeGen/X86/atomic_op.ll: Rename @main to @func. Extra sequences will be inserted to @main as prologue on cygming, to fail.
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llvm-svn: 115611
2010-10-05 11:16:24 +00:00
d77a443631
va_args support for Win64.
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Patch by Cameron!
llvm-svn: 115480
2010-10-03 22:52:07 +00:00
ff85688559
Properly emit stack probe on win64 (for non-mingw targets).
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Based on the patch by Cameron Esfahani!
llvm-svn: 115479
2010-10-03 22:02:38 +00:00
f909b07340
unbreak buildbot
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llvm-svn: 115476
2010-10-03 20:02:48 +00:00
5d9089ae14
Add test to make sure that the MMX intrinsic calls make it out the other end in
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tact.
llvm-svn: 115458
2010-10-03 03:30:30 +00:00
bf73fe5e8d
Need to specify SSE4 for machines which don't have SSE4. The code checked for is generated by SSE4. Otherwise, we get something else.
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llvm-svn: 115352
2010-10-01 21:39:35 +00:00
a39904e6b9
We must check for something.
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llvm-svn: 115309
2010-10-01 10:20:10 +00:00
0e5e4b7b76
Disable tests until I can figure out why they're failing on just two machines but not others.
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llvm-svn: 115308
2010-10-01 10:01:10 +00:00
b3a1022572
Try adding an mtriple.
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llvm-svn: 115307
2010-10-01 09:40:50 +00:00
56f7cd255b
Zap some redundant 'ori $?, $?, 0' from SPU.
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Also remove some code that died in the process.
One now non-existant ori is checked for.
llvm-svn: 115306
2010-10-01 09:20:01 +00:00
3b2b1e7942
FileCheck-ize this test.
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llvm-svn: 115304
2010-10-01 08:55:48 +00:00
9b6853c6eb
FileCheck-ize this test.
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llvm-svn: 115303
2010-10-01 08:50:12 +00:00
a205055857
fix rdar://8494845 + PR8244 - a miscompile exposed by my patch in r101350
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llvm-svn: 115294
2010-10-01 05:36:09 +00:00
f419de0852
One more +sse2.
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llvm-svn: 115293
2010-10-01 05:08:18 +00:00
bb6b961867
Mark all these as needing SSE2. Should fix PPC and
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maybe even Linux.
llvm-svn: 115291
2010-10-01 04:17:55 +00:00
ab60ae3cf3
Disable these tests for now; it's not obvious why they fail on Linux.
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llvm-svn: 115257
2010-10-01 00:59:21 +00:00
c6f17f7420
Make test not sensitive to register choice.
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llvm-svn: 115250
2010-10-01 00:16:17 +00:00
dd224d2333
Massive rewrite of MMX:
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The x86_mmx type is used for MMX intrinsics, parameters and
return values where these use MMX registers, and is also
supported in load, store, and bitcast.
Only the above operations generate MMX instructions, and optimizations
do not operate on or produce MMX intrinsics.
MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into
smaller pieces. Optimizations may occur on these forms and the
result casted back to x86_mmx, provided the result feeds into a
previous existing x86_mmx operation.
The point of all this is prevent optimizations from introducing
MMX operations, which is unsafe due to the EMMS problem.
llvm-svn: 115243
2010-09-30 23:57:10 +00:00
bb995ae261
test/CodeGen/X86/sibcall.ll: Add explicit triplets and remove XFAIL: apple-darwin8.
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llvm-svn: 115215
2010-09-30 22:02:06 +00:00
eb12f49fb7
Try again to disable critical edge splitting in CodeGenPrepare.
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The bug that broke i386 linux has been fixed in r115191.
llvm-svn: 115204
2010-09-30 20:51:52 +00:00
665aa6efcc
When isel is emitting instructions for an x86 target without CMOV, the CFG is
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edited during emission.
If the basic block ends in a switch that gets lowered to a jump table, any
phis at the default edge were getting updated wrong. The jump table data
structure keeps a pointer to the header blocks that wasn't getting updated
after the MBB is split.
This bug was exposed on 32-bit Linux when disabling critical edge splitting in
codegen prepare.
The fix is to uipdate stale MBB pointers whenever a block is split during
emission.
llvm-svn: 115191
2010-09-30 19:44:31 +00:00
645f6c2bef
Tiny patch for proof-of-concept cleanup of ARMAsmPrinter::EmitStartOfAsmFile()
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Small test for sanity check of resulting ARM .s file.
Tested against -r115129.
llvm-svn: 115133
2010-09-30 02:45:56 +00:00
97bf273870
Increase ARM APCS preferred alignment for i64 and f64 from 32 bits to 64 bits.
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LDM/STM instructions can run one cycle faster on some ARM processors if the
memory address is 64-bit aligned. Radar 8489376.
llvm-svn: 115047
2010-09-29 17:54:10 +00:00
c2eb72dc2a
do not compare actual branch labels; this may fix llvm-gcc-x86_64-darwin10-cross-mingw32 buildbot too
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llvm-svn: 115034
2010-09-29 10:45:43 +00:00
d36e3e8850
improve heuristics to find the 'and' corresponding to 'tst' to also catch opportunities on thumb2
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added some doxygen on the way
llvm-svn: 115033
2010-09-29 10:12:08 +00:00
cc91601211
And remove r114997's test.
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llvm-svn: 115003
2010-09-28 23:24:18 +00:00
b0b2c57149
Revert r114997. It was causing a failure on darwin10-selfhost.
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llvm-svn: 115002
2010-09-28 23:11:55 +00:00
d848beb1e5
Fix a FIXME. _foo.eh symbols are currently always exported so that the linker
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knows about them. This is not necessary on 10.6 and later.
llvm-svn: 114997
2010-09-28 22:36:56 +00:00
a3181e2d79
Add a subtarget hook for reporting the misprediction penalty. Use this to provide more precise
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cost modeling for if-conversion. Now if only we had a way to estimate the misprediction probability.
Adjsut CodeGen/ARM/ifcvt10.ll. The pipeline on Cortex-A8 is long enough that it is still profitable
to predicate an ldm, but the shorter pipeline on Cortex-A9 makes it unprofitable.
llvm-svn: 114995
2010-09-28 21:57:50 +00:00
81bdc93bbb
User proper libcall names & condcodes while compiling for ARM EABI.
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Patch by Evzen Muller!
llvm-svn: 114991
2010-09-28 21:39:26 +00:00
88af7d00fc
Part one of switching to using a more sane heuristic for determining if-conversion profitability.
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Rather than having arbitrary cutoffs, actually try to cost model the conversion.
For now, the constants are tuned to more or less match our existing behavior, but these will be
changed to reflect realistic values as this work proceeds.
llvm-svn: 114973
2010-09-28 18:32:13 +00:00
3dc97324c1
Add a command line option "-arm-strict-align" to disallow unaligned memory
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accesses for ARM targets that would otherwise allow it. Radar 8465431.
llvm-svn: 114941
2010-09-28 04:09:35 +00:00
415a7a6fec
Revert "Disable codegen prepare critical edge splitting. Machine instruction passes now"
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This reverts revision 114633. It was breaking llvm-gcc-i386-linux-selfhost.
It seems there is a downstream bug that is exposed by
-cgp-critical-edge-splitting=0. When that bug is fixed, this patch can go back
in.
Note that the changes to tailcallfp2.ll are not reverted. They were good are
required.
llvm-svn: 114859
2010-09-27 18:43:48 +00:00
4f3443e74d
Explicitly disable CGP critical edge splitting for this test so it won't break
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by reenabling it temporarily.
llvm-svn: 114858
2010-09-27 18:43:43 +00:00
f2a279b902
Don't depend on basic block numbering.
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llvm-svn: 114857
2010-09-27 18:43:40 +00:00
9f06f911d1
the latest assembler that runs on powerpc 10.4 machines doesn't
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support aligned comm. Detect when compiling for 10.4 and don't
emit an alignment for comm. THis will hopefully fix PR8198.
llvm-svn: 114817
2010-09-27 06:44:54 +00:00
d6142976de
Add test case for PTX ret instruction
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llvm-svn: 114789
2010-09-25 07:49:54 +00:00
299479020a
Add ret instruction to PTX backend
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llvm-svn: 114788
2010-09-25 07:46:17 +00:00
dbcc4b4d4d
Enable code placement optimization pass for ARM.
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llvm-svn: 114746
2010-09-24 19:07:23 +00:00
7fbbe9a43a
Set alignment operand for NEON VST instructions.
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llvm-svn: 114709
2010-09-23 23:42:37 +00:00
9eeb890172
Set alignment operand for NEON VLD instructions.
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llvm-svn: 114696
2010-09-23 21:43:54 +00:00
794aaa79e2
Disable codegen prepare critical edge splitting. Machine instruction passes now
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break critical edges on demand.
llvm-svn: 114633
2010-09-23 06:55:34 +00:00
3231d13ddd
A select between a constant and zero, when fed by a bit test, can be efficiently
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lowered using a series of shifts.
Fixes <rdar://problem/8285015>.
llvm-svn: 114599
2010-09-22 22:58:22 +00:00
bbb9287080
Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case.
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llvm-svn: 114597
2010-09-22 22:35:21 +00:00
bd85725341
Fix an inconsistency in the x86 backend that led it to reject "calll foo" on
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x86-32: 32-bit calls were named "call" not "calll". 64-bit calls were correctly
named "callq", so this only impacted x86-32.
This fixes rdar://8456370 - llvm-mc rejects 'calll'
This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.
llvm-svn: 114534
2010-09-22 05:49:14 +00:00
8a236b63d8
reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress.
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llvm-svn: 114529
2010-09-22 04:39:11 +00:00
505af598d0
linux has a different stack alignment than the mac, relax this a bit.
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llvm-svn: 114519
2010-09-22 00:46:26 +00:00
54e5329545
give VZEXT_LOAD a memory operand, it now works with segment registers.
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llvm-svn: 114515
2010-09-22 00:34:38 +00:00
07827ba978
revert r114386 now that address modes work correctly, we get a nice
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call through gs-relative memory now.
llvm-svn: 114510
2010-09-22 00:11:31 +00:00
Owen Anderson