Commit Graph

183404 Commits

Author SHA1 Message Date
Moritz Roth f5d0c7c2c0 [Thumb] Make load/store optimizer less conservative.
If it's safe to clobber the condition flags, we can do a few extra things:
it's then possible to reset the base register writeback using a SUBS, so
we can try to merge even if the base register isn't dead after the merged
instruction.

This is effectively a (heavily bug-fixed) rewrite of r208992.

llvm-svn: 218386
2014-09-24 16:35:50 +00:00
David Blaikie 7f0786587f Constify a functor's function call operator because it can/should be.
Patch by Graham Lee (graham@iamleeg.com)!

llvm-svn: 218385
2014-09-24 16:35:29 +00:00
Fariborz Jahanian 945a08d7cd Patch to allow mangling of microsoft’s __uuidof expression for the Itanium ABI
when under -fms-extensions. Reviewed by John McCall.
//rdar://17784718

llvm-svn: 218384
2014-09-24 16:28:40 +00:00
Todd Fiala d5635cdd7f Adjust to LLVM JIT API change
Those wrapper functions seems not used by lldb... Removed

Reference for

replacing JITMemoryManager with SectionMemoryManager
replacing "llvm::JITMemoryManager::CreateDefaultMemManager()" with "new llvm::SectionMemoryManager()"
http://llvm.org/viewvc/llvm-project/llvm/trunk/tools/llvm-jitlistener/llvm-jitlistener.cpp?r1=218316&r2=218315&pathrev=218316

Change by Tong Shen.

Tested:
Ubuntu 14.04 x86_64
MacOSX 10.9.5 with Xcode Version 6.1 (6A1030) (Beta)

llvm-svn: 218383
2014-09-24 15:55:47 +00:00
Oliver Stannard 1ae8b476f4 [Thumb] 32-bit encodings of 'cps' are not valid for v7M
v7M only allows the 16-bit encoding of the 'cps' (Change Processor
State) instruction, and does not have the 32-bit encoding which is
valid from v6T2 onwards.

llvm-svn: 218382
2014-09-24 14:20:01 +00:00
Aaron Ballman f086a14d53 Silencing an "enumeral and non-enumeral type in conditional expression" warning. NFC.
llvm-svn: 218381
2014-09-24 13:54:56 +00:00
Benjamin Kramer ce246a13ea Replace a hand-written suffix compare with std::lexicographical_compare.
No functionality change.

llvm-svn: 218380
2014-09-24 13:19:28 +00:00
Benjamin Kramer 90e0fd8f7f Clean up ClangTool's argument adjuster handling a bit with unique_ptr.
Make the dtor non-virtual while there. No functionality change.

llvm-svn: 218379
2014-09-24 11:47:42 +00:00
David Majnemer ac0b30e6cb Sema: Inherit the flexible array property from struct fields
A record which contains a flexible array member is itself a flexible
array member.  A struct which contains such a record should also
consider itself to be a flexible array member.

llvm-svn: 218378
2014-09-24 11:04:09 +00:00
Chandler Carruth e7e9c04ddf [x86] Teach the instruction lowering to add comments describing constant
pool data being loaded into a vector register.

The comments take the form of:

  # ymm0 = [a,b,c,d,...]
  # xmm1 = <x,y,z...>

The []s are used for generic sequential data and the <>s are used for
specifically ConstantVector loads. Undef elements are printed as the
letter 'u', integers in decimal, and floating point values as floating
point values. Suggestions on improving the formatting or other aspects
of the display are very welcome.

My primary use case for this is to be able to FileCheck test masks
passed to vector shuffle instructions in-register. It isn't fantastic
for that (no decoding special zeroing semantics or other tricks), but it
at least puts the mask onto an instruction line that could reasonably be
checked. I've updated many of the new vector shuffle lowering tests to
leverage this in their test cases so that we're actually checking the
shuffle masks remain as expected.

Before implementing this, I tried a *bunch* of different approaches.
I looked into teaching the MCInstLower code to scan up the basic block
and find a definition of a register used in a shuffle instruction and
then decode that, but this seems incredibly brittle and complex.
I talked to Hal a lot about the "right" way to do this: attach the raw
shuffle mask to the instruction itself in some form of unencoded
operands, and then use that to emit the comments. I still think that's
the optimal solution here, but it proved to be beyond what I'm up for
here. In particular, it seems likely best done by completing the
plumbing of metadata through these layers and attaching the shuffle mask
in metadata which could have fully automatic dropping when encoding an
actual instruction.

llvm-svn: 218377
2014-09-24 09:39:41 +00:00
Robert Khasanov ea13042cf2 [x86] Fixed argument types in intrinsics:
_addcarryx_u64
_addcarry_u64
_subborrow_u64

Thanks Pasi Parviainen for notice.

llvm-svn: 218376
2014-09-24 06:45:23 +00:00
Michael Liao d120916ca7 Allow BB duplication threshold to be adjusted through JumpThreading's ctor
- BB duplication may not be desired on targets where there is no or small
  branch penalty and code duplication needs restrict control.

llvm-svn: 218375
2014-09-24 04:59:06 +00:00
NAKAMURA Takumi f744ad43e1 Windows/Host.inc: Reformat the header to fit 80-col.
llvm-svn: 218374
2014-09-24 04:45:14 +00:00
NAKAMURA Takumi 239a226dea Unix/Host.inc: Remove <cstdlib>. It has been unused for a long time.
llvm-svn: 218373
2014-09-24 04:45:02 +00:00
Nico Weber 28d692d30e Mark module atomic as cplusplus11.
With clang, the header atomic requires __has_feature(cxx_atomic), which is only
true in c++11 mode. Because of this, when using modules in c++98 with libc++
compilation of the std module would fail without this change, PR21002.

(With gcc, only gcc4.7+ is needed, no c++11. But gcc doesn't have modules yet,
and the module.modulemap language can't express things like "this is only
required if the compiler is clang". If gcc gets module support, we'd probably
have a module.modulemap file for each compiler that libc++ supports?)

llvm-svn: 218372
2014-09-24 04:44:54 +00:00
NAKAMURA Takumi 12abbdaeab Unix/Host.inc: Wrap a comment line in 80-col.
llvm-svn: 218371
2014-09-24 04:44:50 +00:00
NAKAMURA Takumi 3d238b47ec Unix/Host.inc: Remove leading whitespace. It had been here since r56942!
llvm-svn: 218370
2014-09-24 04:44:37 +00:00
NAKAMURA Takumi d4252f925e valgrind/x86_64-pc-linux-gnu.supp: Suppress also /bin/bash.
llvm-svn: 218369
2014-09-24 04:38:20 +00:00
NAKAMURA Takumi 853a1bf82c valgrind/x86_64-pc-linux-gnu.supp: Tweak /bin/sed to let calloc recognized.
llvm-svn: 218368
2014-09-24 04:38:09 +00:00
Steven Wu 566c14eccd Fix the argument index error of __builtin___memccpy_chk
memccpy_check should have source and dest size at arg 3 and 4
rdar://18431336

llvm-svn: 218367
2014-09-24 04:37:33 +00:00
Richard Trieu 78dd725cde Fix an edge case with BinaryOperator's in -Wuninitialized. Add testcases for
the other visitors as well.

llvm-svn: 218366
2014-09-24 03:53:56 +00:00
Nico Weber b10c92001c Follow-up to r218292: Add more REVERTIBLE_TYPE_TRAITs.
r218292 reverted r197496 because it broke things. In addition to breaking
things, r197496 also made all traits starting with __is_ revertible.
Reinstantiate that part of r197496 because code out there (e.g. libc++) depends
on this behavior. Fixes PR21045.

llvm-svn: 218365
2014-09-24 03:28:54 +00:00
Jiangning Liu 3b096172cf Clear PreferredExtendType for in each function-specific state FunctionLoweringInfo.
llvm-svn: 218364
2014-09-24 03:22:56 +00:00
Chandler Carruth 7b688c6884 [x86] More refactoring of the shuffle comment emission. The previous
attempt didn't work out so well. It looks like it will be much better
for introducing extra logic to find a shuffle mask if the finding logic
is totally separate. This also makes it easy to sink the opcode logic
completely out of the routine so we don't re-dispatch across it.

Still no functionality changed.

llvm-svn: 218363
2014-09-24 03:06:37 +00:00
Chandler Carruth edf50212df [x86] Bypass the shuffle mask comment generation when not using verbose
asm. This can be somewhat expensive and there is no reason to do it
outside of tests or debugging sessions. I'm also likely to make it
significantly more expensive to support more styles of shuffles.

llvm-svn: 218362
2014-09-24 03:06:34 +00:00
Chandler Carruth ab8b37a9d2 [x86] Hoist the logic for extracting the relevant bits of information
from the MachineInstr into the caller which is already doing a switch
over the instruction.

This will make it more clear how to compute different operands to feed
the comment selection for example.

Also, in a drive-by-fix, don't append an empty comment string (which is
a no-op ultimately).

No functionality changed.

llvm-svn: 218361
2014-09-24 02:24:41 +00:00
Matt Arsenault 2c41987490 R600/SI: Add new helper isSGPRClassID
Move these into header since they are trivial

llvm-svn: 218360
2014-09-24 02:17:12 +00:00
Matt Arsenault 262407bc2f R600/SI: Fix hardcoded and wrong operand numbers.
Also fix leftover debug printing

llvm-svn: 218359
2014-09-24 02:17:09 +00:00
Matt Arsenault 69612d6027 R600/SI: Enable named operand table for SALU instructions
llvm-svn: 218358
2014-09-24 02:17:06 +00:00
Chandler Carruth 0b682d42de [x86] Start refactoring the comment printing logic in the MC lowering of
vector shuffles.

This is just the beginning by hoisting it into its own function and
making use of early exit to dramatically simplify the flow of the
function. I'm going to be incrementally refactoring this until it is
a bit less magical how this applies to other instructions, and I can
teach it how to dig a shuffle mask out of a register. Then I plan to
hook it up to VPERMD so we get our mask comments for it.

No functionality changed yet.

llvm-svn: 218357
2014-09-24 02:16:12 +00:00
Matt Arsenault 3e0effa223 R600/SI: Fix weird CHECK-DAG usage
This prevents these from failing in a future commit.

llvm-svn: 218356
2014-09-24 02:14:26 +00:00
Rui Ueyama a370c3ee35 [PECOFF] Exported name should match C++ mangled name
Currently you can omit the leading underscore from exported
symbol name. LLD will look for mangled name for you. But it won't
look for C++ mangled name.

This patch is to support that.

If "sym" is specified to be exported, the linker looks for not
only "sym", but also "_sym" and "?sym@@<whatever>", so that you
can export a C++ function without decorating it.

llvm-svn: 218355
2014-09-24 02:01:10 +00:00
Rui Ueyama 359a47cee6 [PECOFF] Keep renamed undefined symbol name in export descriptor
Exported symbol name resolution is two-pass. In the first pass,
we try to resolve that as a regular undefined symbol. If it fails,
we look for mangled name for the symbol and rename the undefined
symbol and try again.

After all name resolution is done, we look for an atom for each
exported symbol again, to construct the export table. In this
process we try the regular names first, and then try mangled names.
But at this moment we should have knew which name is correct.

This patch is to keep the information we get in the first process
to use it later.

llvm-svn: 218354
2014-09-24 01:44:59 +00:00
Tom Stellard 744b99b476 R600/SI: Enable selecting SALU inside branches
We can do this now that the FixSGPRLiveRanges pass is working.

llvm-svn: 218353
2014-09-24 01:33:28 +00:00
Tom Stellard deb3f9e643 R600/SI: Move PHIs that define SGPRs to the VALU in most cases
This fixes a bug that is uncovered by a future commit and will
be tested by the test/CodeGen/R600/sgpr-control-flow.ll test case.

llvm-svn: 218352
2014-09-24 01:33:26 +00:00
Tom Stellard 60024a0558 R600/SI: Fix the FixSGPRLiveRanges pass
The previous implementation was extending the live range of SGPRs
by modifying the live intervals directly.  This was causing a lot
of machine verification errors when the machine scheduler was enabled.

The new implementation adds pseudo instructions with implicit uses to
extend the live ranges of SGPRs, which works much better.

llvm-svn: 218351
2014-09-24 01:33:24 +00:00
Tom Stellard be507fb5d3 R600/SI: Mark EXEC_LO and EXEC_HI as reserved
These registers can be allocated and used like other 32-bit registers,
but it seems like a likely source for bugs.

llvm-svn: 218350
2014-09-24 01:33:23 +00:00
Tom Stellard 9a88593ed0 R600/SI: Fix SIRegisterInfo::getPhysRegSubReg()
Correctly handle special registers: EXEC, EXEC_LO, EXEC_HI, VCC_LO,
VCC_HI, and M0.  The previous implementation would assertion fail
when passed these registers.

llvm-svn: 218349
2014-09-24 01:33:22 +00:00
Tom Stellard 96468903d4 R600/SI: Implement VGPR register spilling for compute at -O0 v3
VGPRs are spilled to LDS.  This still needs more testing, but
we need to at least enable it at -O0, because the fast register
allocator spills all registers that are live at the end of blocks
and without this some future commits will break the
flat-address-space.ll test.

v2: Only calculate thread id once

v3: Move insertion of spill instructions to
    SIRegisterInfo::eliminateFrameIndex()
llvm-svn: 218348
2014-09-24 01:33:17 +00:00
Chandler Carruth 9bd10e7492 [x86] Teach the new vector shuffle lowering to lower v8i32 shuffles with
the native AVX2 instructions.

Note that the test case is really frustrating here because VPERMD
requires the mask to be in the register input and we don't produce
a comment looking through that to the constant pool. I'm going to
attempt to improve this in a subsequent commit, but not sure if I will
succeed.

llvm-svn: 218347
2014-09-24 01:24:44 +00:00
Chandler Carruth fd11815a7d [x86] Fix a really terrible bug in the repeated 128-bin-lane shuffle
detection. It was incorrectly handling undef lanes by actually treating
an undef lane in the first 128-bit lane as a *numeric* shuffle value.

Fortunately, this almost always DTRT and disabled detecting repeated
patterns. But not always. =/ This patch introduces a much more
principled approach and fixes the miscompiles I spotted by inspection
previously.

llvm-svn: 218346
2014-09-24 01:03:57 +00:00
Rui Ueyama de18f9657b [PECOFF] Keep unmangled name in the export table descriptor
The export table descriptor is a data structure to keep information
about the export table. It contains a symbol name, and the name may
or may not be mangled.

We need unmangled names for the export table, so we demangle them
before writing them to the export table.

Obviously this is not a correct round-trip conversion. That could
drop a leading underscore from a symbol because that's
indistinguishable from a mangled name.

What we need to do is to keep unmangled names. This patch does that.

llvm-svn: 218345
2014-09-24 00:55:15 +00:00
Rui Ueyama 251d9a34e2 [PECOFF] Simplify /machine option handling
/machine:ebc was previously recognized but rejected. Unknown architecture
names were handled differently but eventually rejected too. We don't need
to distinguish them.

llvm-svn: 218344
2014-09-24 00:21:45 +00:00
Rui Ueyama 75c0127bb3 [PECOFF] Change export table type.
This patch changes the type of export table set from std::set to
std::vector. The new code is slightly inefficient, but because
export table elements are actually mutable, std::vector is better
here. No functionality change.

llvm-svn: 218343
2014-09-24 00:09:36 +00:00
Rui Ueyama 7ea46bab26 [PECOFF] Fix duplicate /export options
If two or more /export options are given for the same symbol, we should
always print a warning message and use the first one regardless of other
parameters.
Previously there was a case that the first parameter is not used.

llvm-svn: 218342
2014-09-23 23:49:41 +00:00
Robin Morisset dc1b248ccf Fix swift-atomics testcase
This testcase was not testing what it meant: because there were only two checks for
dmb {{ish}} in the second function, it could have missed a bug where one of the three
required dmb {{ish}} became dmb {{ishst}}. As I was fixing it, I also added
CHECK-LABELs to make it a bit less brittle.

llvm-svn: 218341
2014-09-23 23:18:01 +00:00
David Majnemer c2e6753958 MS ABI: Pure virtual functions don't contribute to vtordisps
Usually, overriding a virtual function defined in a virtual base
required emission of a vtordisp slot in the record.  However no vtordisp
is needed if the overriding function is pure; it should be impossible to
observe the pure virtual method.

This fixes PR21046.

llvm-svn: 218340
2014-09-23 22:58:15 +00:00
Richard Trieu e396ba6bb0 Improve -Wuninitialized to take into account field ordering with initializer
lists.  Since the fields are inititalized one at a time, using a field with
lower index to initialize a higher indexed field should not be warned on.

llvm-svn: 218339
2014-09-23 22:52:42 +00:00
Chandler Carruth df2e421845 [x86] Teach the new vector shuffle lowering to lower v4i64 vector
shuffles using the AVX2 instructions. This is the first step of cutting
in real AVX2 support.

Note that I have spotted at least one bug in the test cases already, but
I suspect it was already present and just is getting surfaced. Will
investigate next.

llvm-svn: 218338
2014-09-23 22:39:02 +00:00
Reid Kleckner 78927e884b GlobalOpt: Preserve comdats of unoptimized initializers
Rather than slurping in and splatting out the whole ctor list, preserve
the existing array entries without trying to understand them.  Only
remove the entries that we know we can optimize away.  This way we don't
need to wire through priority and comdats or anything else we might add.

Fixes a linker issue where the .init_array or .ctors entry would point
to discarded initialization code if the comdat group from the TU with
the faulty global_ctors entry was dropped.

llvm-svn: 218337
2014-09-23 22:33:01 +00:00