Commit Graph

384879 Commits

Author SHA1 Message Date
CongzheUalberta f5645ea65f [LoopInterchange] Fix transformation bugs in loop interchange
After loop interchange, the (old) outer loop header should not jump to
`LoopExit`. Note that the old outer loop becomes the new inner loop
after interchange. If we branched to `LoopExit` then after interchange
we would jump directly from the (new) inner loop header to `LoopExit`
without executing the rest of (new) outer loop.

This patch modifies adjustLoopBranches() such that the old outer
loop header (which becomes the new inner loop header) jumps to the
old inner loop latch which becomes the new outer loop latch after
interchange.

Reviewed By: bmahjour

Differential Revision: https://reviews.llvm.org/D98475
2021-04-07 20:55:44 -04:00
Craig Topper 5f6b3d1833 [RISCV] Use multiclass inheritance to simplify some of riscv_vector.td. NFCI
We don't need to instantiate single multiclasses inside of
other multiclasses. We can use inheritance and save writing 'defm ""'.

Reviewed By: khchen

Differential Revision: https://reviews.llvm.org/D100074
2021-04-07 17:33:21 -07:00
Jez Ng d9065fe8ea [lld-macho] Parallelize __LINKEDIT generation
Benchmarking chromium_framework on a 3.2 GHz 16-Core Intel Xeon W Mac Pro:

      N           Min           Max        Median           Avg        Stddev
  x  20          4.33          4.42          4.37          4.37   0.021026299
  +  20          4.12          4.23          4.18         4.175   0.035318103
  Difference at 95.0% confidence
    -0.195 +/- 0.0186025
    -4.46224% +/- 0.425686%
    (Student's t, pooled s = 0.0290644)

Reviewed By: #lld-macho, gkm

Differential Revision: https://reviews.llvm.org/D99998
2021-04-07 19:55:52 -04:00
Stanislav Mekhanoshin 37878de503 Disable use of SCC bit from asm
Differential Revision: https://reviews.llvm.org/D100069
2021-04-07 15:32:17 -07:00
Tony Tye 4658cd4c18 [AMDGPU] Update gfx90a memory model support
Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D100070
2021-04-07 22:17:58 +00:00
Stanislav Mekhanoshin d5d412f2ae [AMDGPU] Split GCNRegBankReassign
Allow pass to work separately with SGPR, VGPR registers or both.
This is NFC now but will be needed to split RA for separate
SGPR and VGPR passes.

Differential Revision: https://reviews.llvm.org/D100063
2021-04-07 14:45:13 -07:00
Florian Hahn 0056e7e15a
[BasicAA] Add another GEP modulo test with shl with odd op. 2021-04-07 22:31:51 +01:00
Sanjay Patel c0bbd0cc35 [InstCombine] fold not ops around min/max intrinsics
This is another step towards parity with the existing
cmp+select folds (see D98152).
2021-04-07 17:31:36 -04:00
Sanjay Patel aca2613330 [InstCombine] add test for min/max intrinsic with not ops; NFC 2021-04-07 17:31:36 -04:00
Shafik Yaghmour 79ac5bbb96 [LLDB] Clarifying the documentation for variable formatting wrt to qualifiers and adding a test that demonstrates this
When looking up user specified formatters qualifiers are removed from types before matching,
I have added a clarifying example to the document and added an example to a relevant test to demonstrate this behavior.

Differential Revision: https://reviews.llvm.org/D99827
2021-04-07 14:29:12 -07:00
Craig Topper 56ea2e2fdd [RISCV] Add a special case to lowerSELECT for select of 2 constants with a SETLT condition.
If the constants have a difference of 1 we can convert one to
the other by adding or subtracting the condition.

We have a DAG combine for this, but it only runs before type
legalization. If the select is introduced later during type
legalization or op legalization we will miss it.

We don't need a specific condition, but some conditions are
harder to materialize than others on RISCV. I know that SETLT
will be a single instruction and it is what is used by the
motivating pattern from signed saturating add/sub.

Differential Revision: https://reviews.llvm.org/D99021
2021-04-07 13:47:17 -07:00
Louis Dionne 2da6ce60a5 [libc++abi] Adjust XFAIL for misaligned exception header on ARM
On ARM, the alignment has always been the right one, so this test never
fails.
2021-04-07 16:14:50 -04:00
Jinsong Ji a723310b41 [Driver][test] Test intended target only
6fe7de90b9 changed GNU toolchain,
and added new RUN line to test expected behavior.

The change is for GNU toolchain only, so this will fail other toolchain,
eg: AIX.

Update the test with `-target` to test GNU tool chain only.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D99901
2021-04-07 20:08:26 +00:00
Vy Nguyen db851dfb49 [lld-macho] Make time-trace* options more permissive.
If either `time-trace-granularity` or `time-trace-file` is specified, then don't make users specify `-time-trace`.
It seems silly that I have to type all three options, eg, `-time-trace -time-trace-file=- -time-trace-granularity=...`.

Differential Revision: https://reviews.llvm.org/D100011
2021-04-07 16:00:20 -04:00
Jennifer Yu ebf2dc3328 Fix missing generate capture expression for novariants condition. 2021-04-07 12:35:49 -07:00
Saurabh Jha 7d8513b7f2 [clang] Move int <-> float scalar conversion to a separate function
As prelude to this patch https://reviews.llvm.org/D99037, we want to
move the int-float conversion
into a separate function that can be reused by matrix cast

Differential Revision: https://reviews.llvm.org/D100051
2021-04-07 12:34:16 -07:00
Haruki Imai 39ee9fd8c1 [mlir] Fixed alignment attribute of alloc constant folding.
When allocLikeOp is updated in alloc constant folding,
alighnment attribute was ignored. This patch fixes it.

Signed-off-by: Haruki Imai <imaihal@jp.ibm.com>

Reviewed By: mehdi_amini

Differential Revision: https://reviews.llvm.org/D99882
2021-04-07 19:28:49 +00:00
Paul Robinson 676a9ab5e4 Remove .gitignore entries not relevant in the monorepo.
Differential Revision: https://reviews.llvm.org/D100049
2021-04-07 12:25:02 -07:00
Craig Topper 9895285191 [RISCV] Replace 'return ReplaceNode' with 'ReplaceNode; return;' NFC
ReplaceNode is a void function as is the function that we were
doing this in. While this is valid code, it was a bit confusing.
2021-04-07 12:18:41 -07:00
Florian Hahn 6e36859a84
[BasicAA] Extend test coverage for GEP modulo logic.
Add a few additional test cases which combine multiplies with
powers-of-2, different wrapping flags.
2021-04-07 20:13:35 +01:00
Jonas Hahnfeld 6415f424bc [AArch64] Materialize FP constant in code for large code model
When using the large code model with FastISel (for example via
clang -O0 which adds the optnone attribute), FP constants could
still be materialized using adrp + ldr. Unconditionally enable
the existing path for MachO to materialize the constant in code.

For testing, restore literal_pools_float.ll to exercise the constant
pool and add two optnone-functions that return a float and a double,
respectively. Consolidate fpimm.ll and add a new fast-isel-fpimm.ll
to check the code paths taken with FastISel.

Differential Revision: https://reviews.llvm.org/D99607
2021-04-07 21:02:05 +02:00
Arthur Eubanks 90af134473 Revert "[AsmPrinter] Delete dead takeDeletedSymbsForFunction()"
This reverts commit 9583a3f262.

This wasn't NFC as initially thought. Needed for D99707.
2021-04-07 11:40:44 -07:00
Abhina Sreeskantharajan 5c8462b5da [Windows] Remove global OF_None flag for Windows in ToolOutputFiles
Since we have created a new OF_TextWithCRLF flag, we no longer need to worry about OF_Text flag turning on CRLF translation. I can remove this workaround I added to globally open all ToolOutputFiles as binary on Windows.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D100034
2021-04-07 14:10:04 -04:00
Aaron Ballman 028092eb61 Correct the tablegen logic for MutualExclusions attribute checking.
Just because an attribute is a statement attribute doesn't mean it's
not also a declaration attribute. In Clang, there are not currently any
DeclOrStmtAttr attributes that require mutual exclusion checking, but
downstream clients discovered this issue.
2021-04-07 14:04:08 -04:00
Vy Nguyen ffc65824f0 [lld-macho][nfc] Minor refactoring + clang-tidy fixes
- use "empty()" instead of "size()"
- refactor the re-export code so it doesn't create a new vector every time.

Differential Revision: https://reviews.llvm.org/D100019
2021-04-07 13:55:52 -04:00
Jordan Rupprecht f49a4440d3 [lldb][Editline] Fix crash when navigating through empty command history.
An empty history entry can happen by entering the expression evaluator an immediately hitting enter:

```
$ lldb
(lldb) e
Enter expressions, then terminate with an empty line to evaluate:
  1:  <hit enter>
```

The next time the user enters the expression evaluator, if they hit the up arrow to load the previous expression, lldb crashes. This patch treats empty history sessions as a single expression of zero length, instead of an empty list of expressions.

Fixes http://llvm.org/PR49845.

Differential Revision: https://reviews.llvm.org/D100048
2021-04-07 10:48:47 -07:00
Craig Topper f087d7544a [RISCV] Support vslide1up/down intrinsics for SEW=64 on RV32.
This can't use our normal strategy of splatting the scalar and using
a .vv operation instead of .vx.

Instead this patch bitcasts the vector to the equivalent SEW=32
vector and inserts the scalar parts using two vslide1up/down. We
do that unmasked and apply the mask separately at the end with
a vmerge.

For vslide1up there maybe some other options here like getting
i64 into element 0 and using vslideup.vi with this vector as
vd and the original source as vs1. Masking would still need to
be done afterwards.

That idea doesn't work for vslide1down. We need to slidedown and
then insert a single scalar at vl-1 which we could do with a
vslideup, but that assumes vl > 0 which I don't think we can assume.

The i32 double slide1down implemented here is the best I could come
up with and I just made vslide1up consistent.

Reviewed By: frasercrmck

Differential Revision: https://reviews.llvm.org/D99910
2021-04-07 10:44:53 -07:00
Aaron En Ye Shi df59850038 [HIP] Fix rocm-detect.hip test path
The ROCm installation directory may be another
directory, llvm/ inside the build directory.

Reviewed By: yaxunl

Differential Revision: https://reviews.llvm.org/D100045
2021-04-07 17:20:59 +00:00
Craig Topper 67953311e2 [SelectionDAG] Teach SelectionDAG::FoldConstantArithmetic to handle SPLAT_VECTOR
This allows FoldConstantArithmetic to handle SPLAT_VECTOR in
addition to BUILD_VECTOR. This allows it to support scalable
vectors. I'm also allowing fixed length SPLAT_VECTOR which is
used by some targets, but I'm not familiar enough to write tests
for those targets.

I had to block this function from running on CONCAT_VECTORS to
avoid calling getNode for a CONCAT_VECTORS of 2 scalars.
This can happen because the 2 operand getNode calls this
function for any opcode. Previously we were protected because
CONCAT_VECTORs of BUILD_VECTOR is folded to a larger BUILD_VECTOR
before that call. But it's not always possible to fold a CONCAT_VECTORS
of SPLAT_VECTORs, and we don't even try.

This fixes PR49781 where DAG combine thought constant folding
should be possible, but FoldConstantArithmetic couldn't do it.

Reviewed By: david-arm

Differential Revision: https://reviews.llvm.org/D99682
2021-04-07 10:03:33 -07:00
Craig Topper 5fc0e98d9a [LoopIdiomRecognize] Minor cleanups to the FFS idiom matching. NFC
-Make sure of the CreateShl/LShr/AShr methods that take a uint64_t
instead of creating a ConstantInt for 1 ourselves.
-Use Builder.getInt1 or ConstantInt::getBool instead of a conditional.
-Pull out repeated calls to getType.
2021-04-07 10:03:14 -07:00
Aart Bik 3acf49829c [mlir][sparse] support integral types i32,i16,i8 for *numerical* values
Some sparse matrices operate on integral values (in contrast with the common
f32 and f64 values). This CL expands the compiler and runtime support to deal
with several common type combinations.

Reviewed By: bixia

Differential Revision: https://reviews.llvm.org/D99999
2021-04-07 10:01:37 -07:00
Dimitry Andric b3e9b07a7d Avoid testing for libc++ internal macros after D99834
As D99834 was meant specifically for FreeBSD, which still uses the older
non-trivial std::pair copy constructors, test for `__FreeBSD__` instead
of relying on a macro which is an internal detail of libc++.

Noted by Louis Dionne.
2021-04-07 18:52:41 +02:00
Roman Lebedev 24f67473dd
[InstCombine] foldAddWithConstant(): don't deal with non-immediate constants
All of the code that handles general constant here (other than the more
restrictive APInt-dealing code) expects that it is an immediate,
because otherwise we won't actually fold the constants, and increase
instruction count. And it isn't obvious why we'd be okay with
increasing the number of constant expressions,
those still will have to be run..

But after 2829094a8e
this could also cause endless combine loops.
So actually properly restrict this code to immediates.
2021-04-07 19:50:19 +03:00
Mark de Wever 48fa06f70b [libc++] Update contributor documentation.
The document has the following updates:
- Rename 'feature test' to 'feature-test', the latter is the spelling
  used in the Standard.
- Add information how an ABI list can be downloaded from Buildkite.

Differential Revision: https://reviews.llvm.org/D99290
2021-04-07 18:33:27 +02:00
Sanjay Patel 1894c6c59e [InstCombine] avoid infinite loop from partial undef vectors
This fixes the examples from
D99674 and
https://llvm.org/PR49878

The matchers succeed on partial undef/poison vector constants,
but the transform creates a full 'not' (-1) constant, so it
would undo a demanded vector elements change triggered by the
extractelement.

Differential Revision: https://reviews.llvm.org/D100044
2021-04-07 12:18:12 -04:00
Christopher Di Bella 920c0f7e09 [libcxx] adds __cpp_lib_concepts feature-test macro
Also adjusts C++20 status paper to indicate full concepts support.

Depends on D96477, D99817.

Differential Revision: https://reviews.llvm.org/D99805
2021-04-07 16:14:45 +00:00
Christopher Di Bella c7ad020099 [libcxx] adds remaining callable concepts
* `std::predicate`
* `std::relation`
* `std::equivalence_relation`
* `std::strict_weak_order`

Implements parts of:
    - P0898R3 Standard Library Concepts
    - P1754 Rename concepts to standard_case for C++20, while we still can

Differential Revision: https://reviews.llvm.org/D96477
2021-04-07 16:14:45 +00:00
Jez Ng 982e3c0510 [lld-macho] Sibling N_SO symbols must have the empty string
We had been giving them a string index of zero, which actually corresponds to a
string with a single space due to {D89639}.

This was far from obvious in the old test because llvm-nm doesn't quote the
symbol names, making the empty string look identical to a string of a single
space. `dsymutil -s` quotes its strings, so I've changed the test accordingly.

Fixes llvm.org/PR48714. Thanks @clayborg for the tips!

Reviewed By: clayborg

Differential Revision: https://reviews.llvm.org/D100003
2021-04-07 12:08:14 -04:00
Jez Ng d855a727bb [lld-macho][nfc] Add test for ARM64 stubs
Reviewed By: #lld-macho, gkm

Differential Revision: https://reviews.llvm.org/D99813
2021-04-07 12:08:12 -04:00
wlei 6d5132b426 [CSSPGO] Fix incorrect probe distribution factor computation in top-down inliner
We see a regression related to low probe factor(0.01) which prevents some callsites being promoted in ICPPass and later cause the missing inline in CGSCC inliner. The root cause is due to redundant(the second) multiplication of the probe factor and this change try to fix it.

`Sum` does multiply a factor right after findCallSamples but later when using as the parameter in setProbeDistributionFactor, it multiplies one again.

This change could get ~2% perf back on mcf benchmark. In mcf, previously the corresponding factor is 1 and it's the recent feature introducing the <1 factor then trigger this bug.

Reviewed By: hoy, wenlei

Differential Revision: https://reviews.llvm.org/D99787
2021-04-07 08:48:59 -07:00
Simon Pilgrim 93fb72575f [X86][AVX] Add HADD lane crossing test
This used to work before rG77d625f8d8aa, but we now merge the shuffles across the fadd resulting in a hadd that requires a lane crossing post shuffle, which we don't permit on AVX1 targets
2021-04-07 16:43:47 +01:00
Nicolas Vasilache 3b460f8cc0 [mlir] Export python-related .cmake files
This allows downstream projects to build python extensions using the same macros as MLIR.

Differential Revision: https://reviews.llvm.org/D100040
2021-04-07 15:25:17 +00:00
Abhina Sreeskantharajan 1bcf58b213 [SystemZ][z/OS][TableGen] TableGen files should be text
This patch sets tablegen files as text. It should have no effect on Windows after this patch landed https://reviews.llvm.org/rG82b3e28e836d2f5c8cfd6e1047b93c088522365a.

Reviewed By: anirudhp

Differential Revision: https://reviews.llvm.org/D100036
2021-04-07 11:23:00 -04:00
Jacques Pienaar 628dda08b8 [mlir,shape] Update min/max op description 2021-04-07 08:21:15 -07:00
Sander de Smalen 672f673004 [SVE] Remove checks for warnings in scalable-vector tests.
After D98856 these tests will by default break (fatal_error) if any of
the wrong interfaces are used, so there's no longer a need to have a
RUN line that checks for a warning message emitted by the compiler.
2021-04-07 15:59:32 +01:00
Sam Clegg f23b259e18 [WebAssembly] Improve error messages regarding missing indirect function table. NFC
Use report_fatal_error here since this is an internal error, and not
something the user can/should be trying to fix.

Also distinguish between the symbol being missing and the symbol having
the wrong type.

We have a failure internally where the symbol is missing.  Currently
trying to reduce the test case to something we can attach to an llvm
bug.

Differential Revision: https://reviews.llvm.org/D99960
2021-04-07 07:58:43 -07:00
Sebastian Neubauer 2dc6be5209 [AMDGPU] Update SGPRSpillVGPRCSR name. NFC
The struct is used for both, callee and caller-save registers now.
The frame index is not set for entrypoints, as we do not need to save
the registers then.
Update the struct name to reflect that.

Differential Revision: https://reviews.llvm.org/D99722
2021-04-07 16:30:40 +02:00
Jingu Kang 798b0fd36b [NPM] Fix typo inisLTOPreLink for loop rotate
Differential Revision: https://reviews.llvm.org/D100033
2021-04-07 15:08:37 +01:00
Nico Weber c22b09debd Revert "[clang] Speedup line offset mapping computation"
This reverts commit 6951b72334.
Breaks several bots, see comments on https://reviews.llvm.org/D99409
2021-04-07 09:42:11 -04:00
Simon Pilgrim 302e748065 [X86] Improve optimizeCompareInstr for signed comparisons after AND/OR/XOR instructions
Extend D94856 to handle 'and', 'or' and 'xor' instructions as well

We still fail on many i8/i16 cases as the test and the logic-op are performed on different widths
2021-04-07 14:28:42 +01:00