192f27cb5c
really fix run line
...
llvm-svn: 57889
2008-10-21 03:55:19 +00:00
b4ee2aebb5
fix run line
...
llvm-svn: 57888
2008-10-21 03:54:49 +00:00
0b641e4718
remove some unneeded eh generation
...
llvm-svn: 57887
2008-10-21 03:49:19 +00:00
269246b034
Don't create TargetGlobalAddress nodes with offsets that don't fit
...
in the 32-bit signed offset field of addresses. Even though this
may be intended, some linkers refuse to relocate code where the
relocated address computation overflows.
Also, fix the sign-extension of constant offsets to use the
actual pointer size, rather than the size of the GlobalAddress
node, which may be different, for example on x86-64 where MVT::i32
is used when the address is being fit into the 32-bit displacement
field.
llvm-svn: 57885
2008-10-21 03:38:42 +00:00
97d95d6d85
Optimized FCMP_OEQ and FCMP_UNE for x86.
...
Where previously LLVM might emit code like this:
ucomisd %xmm1, %xmm0
setne %al
setp %cl
orb %al, %cl
jne .LBB4_2
it now emits this:
ucomisd %xmm1, %xmm0
jne .LBB4_2
jp .LBB4_2
It has fewer instructions and uses fewer registers, but it does
have more branches. And in the case that this code is followed by
a non-fallthrough edge, it may be followed by a jmp instruction,
resulting in three branch instructions in sequence. Some effort
is made to avoid this situation.
To achieve this, X86ISelLowering.cpp now recognizes FCMP_OEQ and
FCMP_UNE in lowered form, and replace them with code that emits
two branches, except in the case where it would require converting
a fall-through edge to an explicit branch.
Also, X86InstrInfo.cpp's branch analysis and transform code now
knows now to handle blocks with multiple conditional branches. It
uses loops instead of having fixed checks for up to two
instructions. It can now analyze and transform code generated
from FCMP_OEQ and FCMP_UNE.
llvm-svn: 57873
2008-10-21 03:29:32 +00:00
c835458da9
When the coalescer is doing rematerializing, have it remove
...
the copy instruction from the instruction list before asking the
target to create the new instruction. This gets the old instruction
out of the way so that it doesn't interfere with the target's
rematerialization code. In the case of x86, this helps it find
more cases where EFLAGS is not live.
Also, in the X86InstrInfo.cpp, teach isSafeToClobberEFLAGS to check
to see if it reached the end of the block after scanning each
instruction, instead of just before. This lets it notice when the
end of the block is only two instructions away, without doing any
additional scanning.
These changes allow rematerialization to clobber EFLAGS in more
cases, for example using xor instead of mov to set the return value
to zero in the included testcase.
llvm-svn: 57872
2008-10-21 03:24:31 +00:00
4396e0d2c3
Fix gcc.c-torture/compile/920520-1.c by inserting bitconverts
...
for strange asm conditions earlier. In this case, we have a
double being passed in an integer reg class. Convert to like
sized integer register so that we allocate the right number
for the class (two i32's for the f64 in this case).
llvm-svn: 57862
2008-10-21 00:45:36 +00:00
160e8abd77
Reapply r57699 with a fix to not crash on asms with multiple results. Unlike
...
the previous patch this one actually passes make check.
"Fix PR2356 on PowerPC: if we have an input and output that are tied together
that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand."
llvm-svn: 57771
2008-10-18 18:49:30 +00:00
2fe6bee5b6
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
...
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
llvm-svn: 57748
2008-10-18 02:06:02 +00:00
6de2556205
Revert r57699. It's causing regressions in
...
test/CodeGen/X86/2008-09-17-inline-asm-1.ll
and a few others, and it breaks the llvm-gcc build.
llvm-svn: 57747
2008-10-18 01:03:45 +00:00
94169f1021
Fix PR2898. Spiller delete a store for reuse before it knows for sure the reuse happened.
...
Patch by Lang Hames!
llvm-svn: 57720
2008-10-17 20:56:41 +00:00
c7e65f4377
Fix a bug where the x86 backend would reject 64-bit r constraints when
...
in 32-bit mode instead of assigning a register pair. This has nothing to
do with PR2356, but I happened to notice it while working on it.
llvm-svn: 57704
2008-10-17 17:59:52 +00:00
052092bf9c
Fix PR2356 on PowerPC: if we have an input and output that are tied together
...
that have different sizes (e.g. i32 and i64) make sure to reserve registers for
the bigger operand.
llvm-svn: 57699
2008-10-17 17:52:49 +00:00
00c5d69998
remove an xfailed test.
...
llvm-svn: 57695
2008-10-17 17:26:48 +00:00
e212b970cf
remove this test: it is xfailed anyway, and is failing for a reason
...
other than why it was xfailed.
llvm-svn: 57694
2008-10-17 17:26:19 +00:00
08acb24225
Fix a very subtle spiller bug: UpdateKills should not forget to track defs of aliases.
...
llvm-svn: 57673
2008-10-17 06:16:07 +00:00
ca0546facc
Fun x86 encoding tricks: when adding an immediate value of 128,
...
use a SUB instruction instead of an ADD, because -128 can be
encoded in an 8-bit signed immediate field, while +128 can't be.
This avoids the need for a 32-bit immediate field in this case.
A similar optimization applies to 64-bit adds with 0x80000000,
with the 32-bit signed immediate field.
To support this, teach tablegen how to handle 64-bit constants.
llvm-svn: 57663
2008-10-17 01:33:43 +00:00
a39b0a1f05
Define patterns for shld and shrd that match immediate
...
shift counts, and patterns that match dynamic shift counts
when the subtract is obscured by a truncate node.
Add DAGCombiner support for recognizing rotate patterns
when the shift counts are defined by truncate nodes.
Fix and simplify the code for commuting shld and shrd
instructions to work even when the given instruction doesn't
have a parent, and when the caller needs a new instruction.
These changes allow LLVM to use the shld, shrd, rol, and ror
instructions on x86 to replace equivalent code using two
shifts and an or in many more cases.
llvm-svn: 57662
2008-10-17 01:23:35 +00:00
016f16daf1
Fix this test so it actually runs the grep lines.
...
llvm-svn: 57653
2008-10-16 23:57:54 +00:00
7451f87273
Testcase for PR2762.
...
llvm-svn: 57633
2008-10-16 08:56:46 +00:00
f998a65980
Testcase for PR1638.
...
llvm-svn: 57590
2008-10-15 18:27:15 +00:00
3b0f5e4d61
- Add target lowering hooks that specify which setcc conditions are illegal,
...
i.e. conditions that cannot be checked with a single instruction. For example,
SETONE and SETUEQ on x86.
- Teach legalizer to implement *illegal* setcc as a and / or of a number of
legal setcc nodes. For now, only implement FP conditions. e.g. SETONE is
implemented as SETO & SETNE, SETUEQ is SETUO | SETEQ.
- Move x86 target over.
llvm-svn: 57542
2008-10-15 02:05:31 +00:00
56b6885104
When doing the very-late shift-and address-mode optimization,
...
create a new DAG node to represent the new shift to keep the
DAG consistent, even though it'll almost always be folded into
the address.
If a user of the resulting address has multiple uses, the
nodes may get revisited by a later MatchAddress call, in which
case DAG inconsistencies do matter.
This fixes PR2849.
llvm-svn: 57465
2008-10-13 20:52:04 +00:00
da9b752883
FIX PR2794. Make sure SIGN_EXTEND_INREG nodes introduced by LegalizeSetCCOperands are leglized. Patch by Richard Pennington.
...
llvm-svn: 57460
2008-10-13 18:46:18 +00:00
4c499c4fa6
Also update sub-register intervals after a trivial computation is rematt'ed for a copy instruction. PR2775.
...
llvm-svn: 57458
2008-10-13 18:35:52 +00:00
762f0f53ec
Add a test case for _Complex passed as a FCA.
...
llvm-svn: 57456
2008-10-13 18:13:07 +00:00
2753955fc0
Change CALLSEQ_BEGIN and CALLSEQ_END to take TargetConstant's as
...
parameters instead of raw Constants. This prevents the constants from
being selected by the isel pass, fixing PR2735.
llvm-svn: 57385
2008-10-11 22:08:30 +00:00
a0cce200c5
Add testcase for 'r' inline asm operand
...
llvm-svn: 57361
2008-10-10 20:28:59 +00:00
b36d3b2bb7
This does not fail anymore
...
llvm-svn: 57360
2008-10-10 20:28:32 +00:00
e6b3093b18
Add sparc test for memory operand used in inline asm
...
llvm-svn: 57348
2008-10-10 10:15:33 +00:00
b3692f7d38
This is not failing anymore
...
llvm-svn: 57347
2008-10-10 10:15:18 +00:00
1a84f86271
get CodeGen/Alpha/mul128.ll to work.
...
llvm-svn: 57318
2008-10-09 04:50:56 +00:00
60ad173dfe
Remove -disable-fast-isel. Use cl::boolOrDefault with -fast-isel
...
instead.
So now: -fast-isel or -fast-isel=true enable fast-isel, and
-fast-isel=false disables it. Fast-isel is also on by default
with -fast, and off by default otherwise.
llvm-svn: 57270
2008-10-07 23:00:56 +00:00
b8118fd432
Add a testcase for i256 add. i256 isn't fully supported in
...
codegen right now, but add and subtract work.
llvm-svn: 57260
2008-10-07 20:39:12 +00:00
83f5f40b6a
128 mul test, xfailed
...
llvm-svn: 57250
2008-10-07 17:13:32 +00:00
1699ad9030
Certain patterns involving the "movss" instruction were marked as requiring SSE2, when in reality movss is an SSE1 instruction.
...
llvm-svn: 57246
2008-10-07 16:14:11 +00:00
3a9be150be
Expand arith on machines without carry flags
...
llvm-svn: 57243
2008-10-07 14:15:42 +00:00
315e3c0e64
no need to write the output to the disk
...
llvm-svn: 57232
2008-10-07 04:06:55 +00:00
3b893a905e
Add test case for ADDC ADDE expansion
...
llvm-svn: 57228
2008-10-07 02:30:13 +00:00
6c6729f3a8
Be more precise about which conversions of NaNs
...
are Inexact. (These are not Inexact as defined
by IEEE754, but that seems like a reasonable way
to abstract what happens: information is lost.)
llvm-svn: 57218
2008-10-06 22:59:10 +00:00
94d14f2d45
Fix PR2850 and PR2863. Only generate movddup for 128-bit SSE vector shuffles.
...
llvm-svn: 57210
2008-10-06 21:13:08 +00:00
b52ef06c8c
Revert r56675 - it breaks unwinding runtime everywhere.
...
llvm-svn: 57048
2008-10-04 11:09:36 +00:00
78bb44fcd4
Fix a bug in the local allocator's liveness computation where it
...
was setting kill flags on tied uses in two-address instructions.
The kill flags were causing the allocator to think it could
allocate the use and its tied def in different registers.
llvm-svn: 57039
2008-10-04 00:31:14 +00:00
867d549fce
Handle some 64-bit atomics on x86-32, some of the time.
...
llvm-svn: 56963
2008-10-02 18:53:47 +00:00
88536398ff
Fix a think-o in isSafeToMove. This fixes it from thinking that
...
volatile memory references are safe to move.
llvm-svn: 56948
2008-10-02 15:04:30 +00:00
dfc507d2b5
Disable fast-isel for this test, as it doesn't emit the same
...
number of instructions.
llvm-svn: 56940
2008-10-01 23:48:35 +00:00
1b76f2c40b
Remove OptimizeForSize global. Use function attribute optsize.
...
llvm-svn: 56937
2008-10-01 23:18:38 +00:00
5c8c00af1f
Split this test and move it into target-specific directories.
...
This fixes failures on configurations that don't have one or the
other targets enabled.
llvm-svn: 56926
2008-10-01 19:46:30 +00:00
7354227de0
nounwind-ify this test.
...
llvm-svn: 56918
2008-10-01 15:07:14 +00:00
920f6d588e
Moved this option to the front-end.
...
llvm-svn: 56901
2008-10-01 01:02:18 +00:00
1df16dff64
Use explicit target-triples to unbreak this test on non-darwin systems.
...
llvm-svn: 56896
2008-10-01 00:25:38 +00:00
1782584f56
Just don't transform this memset into "bzero" if no-builtin is specified.
...
llvm-svn: 56888
2008-09-30 22:05:33 +00:00
e818bc159f
- Initialize "--no-builtin" to "false".
...
- Testcase for r56885.
llvm-svn: 56886
2008-09-30 21:40:30 +00:00
9156bd2f48
Re-apply 56835 along with header file changes.
...
llvm-svn: 56848
2008-09-30 15:44:16 +00:00
2b9adce1d0
Revert commit 56835 since it breaks the build.
...
"If a re-materializable instruction has a register
operand, the spiller will change the register operand's
spill weight to HUGE_VAL to avoid it being spilled.
However, if the operand is already in the queue ready
to be spilled, avoid re-materializing it".
llvm-svn: 56837
2008-09-30 10:00:30 +00:00
9469049f7d
If a re-materializable instruction has a register operand, the spiller will change the register operand's spill weight to HUGE_VAL to avoid it being spilled. However, if the operand is already in the queue ready to be spilled, avoid re-materializing it.
...
llvm-svn: 56835
2008-09-30 06:36:58 +00:00
82237f2f42
Fix PR2835. Do not change the width of a volatile load.
...
llvm-svn: 56792
2008-09-29 17:26:18 +00:00
3774b2f292
Re-apply 56683 with fixes.
...
llvm-svn: 56748
2008-09-27 01:56:22 +00:00
9eb525d4f9
Implement function notes as function attributes.
...
llvm-svn: 56716
2008-09-26 23:51:19 +00:00
7d6fa97567
Implement "punpckldq %xmm0, $xmm0" as "pshufd $0x50, %xmm0, %xmm" unless optimizing for code size.
...
llvm-svn: 56711
2008-09-26 23:41:32 +00:00
c966a737c5
Temporarily reverting r56683. This is causing a failure during the build of llvm-gcc:
...
/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.obj/./gcc/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Gir/devel/llvm/clean/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -mmacosx-version-min=10.4 -O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings -Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition -isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2 -D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc -I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include -I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include -I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber -I/Volumes/Gir/devel/llvm/clean/llvm.obj/include -I/Volumes/Gir/devel/llvm/clean/llvm.src/include -fexceptions -fvisibility=hidden -DHIDE_EXPORTS -c ../../llvm-gcc.src/gcc/unwind-dw2-fde-darwin.c -o libgcc/./unwind-dw2-fde-darwin.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) && TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical register live information"), function runOnMachineFunction, file /Volumes/Gir/devel/llvm/clean/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp, line 311.
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:3521:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
{standard input}:3521:symbol: "_dwarf_reg_size_table" can't be undefined in a subtraction expression
{standard input}:3520:non-relocatable subtraction expression, "_dwarf_reg_size_table" minus "L20$pb"
...
llvm-svn: 56703
2008-09-26 22:10:44 +00:00
d77cbe8947
Fix @llvm.frameaddress codegen. FP elimination optimization should be disabled when frame address is desired. Also add support for depth > 0.
...
llvm-svn: 56683
2008-09-26 19:48:35 +00:00
994dd0bbec
Avoid spilling EBP / RBP twice in the prologue.
...
llvm-svn: 56675
2008-09-26 19:14:21 +00:00
9dbe45c000
Prefer movlhps over punpcklqdq, etc. in more cases.
...
llvm-svn: 56627
2008-09-25 23:35:16 +00:00
74c9ed91b0
With sse3 and when the source is a load or has multiple uses, favors movddup over shuffp*, pshufd, etc. Without sse3 or when the source is from a register, make use of movlhps
...
llvm-svn: 56620
2008-09-25 20:50:48 +00:00
c50ada2f56
Accept 'inreg' attribute on x86 functions as
...
meaning sse_regparm (i.e. float/double values go
in XMM0 instead of ST0). Update documentation
to reflect reality.
llvm-svn: 56619
2008-09-25 20:47:45 +00:00
f8ead16b50
Fix patterns for SSE4.1 move and sign extend instructions. Also add instructions which fold VZEXT_MOVL and VZEXT_LOAD.
...
llvm-svn: 56594
2008-09-24 23:27:55 +00:00
86d421df23
Remove SelectionDag early allocation of registers
...
for earlyclobbers. Teach Local RA about earlyclobber,
and add some tests for it.
llvm-svn: 56592
2008-09-24 23:13:09 +00:00
e0add20c1b
Properly handle 'm' inline asm constraints. If a GV is being selected for the addressing mode, it requires the same logic for PIC relative addressing, etc.
...
llvm-svn: 56526
2008-09-24 00:05:32 +00:00
9e9426cb82
Support x86 specific inline asm modifier 'J'.
...
llvm-svn: 56483
2008-09-22 23:57:37 +00:00
796a271c5f
Change the calling convention used when tail call optimization is enabled from CC_X86_32_TailCall to CC_X86_32_FastCC.
...
llvm-svn: 56436
2008-09-22 14:50:07 +00:00
c042000649
Fix PR2808. When regalloc runs out of register, it spill a physical register around the live interval being allocated. Do not continue to try to spill another register, just grab the physical register and move on.
...
llvm-svn: 56381
2008-09-20 01:28:05 +00:00
65502487b7
Clean up the test.
...
llvm-svn: 56380
2008-09-20 01:26:27 +00:00
4730522235
No need to print function stubs for Mac OS X 10.5 and up. Linker will handle it.
...
llvm-svn: 56378
2008-09-20 00:13:45 +00:00
9801ba451a
Refactor X86SelectConstAddr, folding it into X86SelectAddress. This
...
results in better code for globals. Also, unbreak the local CSE for
GlobalValue stub loads.
llvm-svn: 56371
2008-09-19 22:16:54 +00:00
4c0197043c
Re-materalized definition instructions may be dead. Whack them.
...
llvm-svn: 56352
2008-09-19 17:38:47 +00:00
f8610ebebc
Add a bit to mark operands of asm's that conflict
...
with an earlyclobber operand elsewhere. Propagate
this bit and the earlyclobber bit through SDISel.
Change linear-scan RA not to allocate regs in a way
that conflicts with an earlyclobber. See also comments.
llvm-svn: 56290
2008-09-17 21:13:11 +00:00
f3fcd7a464
Unallocatable registers do not have live intervals.
...
llvm-svn: 56287
2008-09-17 18:36:25 +00:00
95e1af217f
Add trampoline support to PPC. GCC simply calls the "__trampoline_setup"
...
function with appropriate parameters. This allows us to support blocks on PPC.
llvm-svn: 56267
2008-09-17 00:30:57 +00:00
68e7735a38
Teach LSR to optimize away SMAX operations for tripcounts in common
...
cases. See the comment above OptimizeSMax for the full story, and
the testcase for an example. This cancels out a pessimization
commonly attributed to indvars, and will allow us to lift some of
the artificial throttles in indvars, rather than add new ones.
llvm-svn: 56230
2008-09-15 21:22:06 +00:00
3c7b9ba547
Re-enable SelectionDAG CSE for calls. It matters in the case of
...
libcalls, as in this testcase on ARM.
llvm-svn: 56226
2008-09-15 19:46:03 +00:00
595229a15a
Added testcase for bswap allegrexel intrinsic
...
llvm-svn: 56225
2008-09-15 19:38:11 +00:00
02acc35abd
Correctly update kill infos after extending a live range and merge 2 val#'s; fix 56165 - do not mark val# copy field if the copy does not define the val#.
...
llvm-svn: 56199
2008-09-15 06:28:41 +00:00
3c12fc4342
On some targets, non-move instructions can become move instructions because of coalescing. e.g.
...
vr2 = OR vr0, vr1
=>
vr2 = OR vr1, vr1 // after coalescing vr0 with vr1
Update the value# of the destination register with the copy instruction if that happens.
llvm-svn: 56165
2008-09-12 18:13:14 +00:00
33ad850d93
Add indirect tail call (function pointer) examples.
...
llvm-svn: 56127
2008-09-11 22:24:28 +00:00
dd45bc25ac
When tailcallopt is enabled all fastcc calls must have an aligned argument stack size. Add a test case.
...
llvm-svn: 56119
2008-09-11 20:28:43 +00:00
5456a37280
Fix PR2748. Avoid coalescing physical register with virtual register which would create illegal extract_subreg. e.g.
...
vr1024 = extract_subreg vr1025, 1
...
vr1024 = mov8rr AH
If vr1024 is coalesced with AH, the extract_subreg is now illegal since AH does not have a super-reg whose sub-register 1 is AH.
llvm-svn: 56118
2008-09-11 20:07:10 +00:00
4c9fbbb511
Fix PR2783 - coalescer bug. Missing a TargetRegisterInfo::isVirtualRegister check.
...
llvm-svn: 56112
2008-09-11 18:40:32 +00:00
b401449ceb
Propagate subreg index when promoting a load to a copy.
...
llvm-svn: 56085
2008-09-11 01:02:12 +00:00
710c3cf36a
Fix a fastcc + sret bug. If fastcc and sret, callee doesn't need to pop the hidden struct ptr; Re-enable fastcc.
...
llvm-svn: 56061
2008-09-10 18:25:29 +00:00
f4e5de4583
Legalizer was missing code that expand fpow to a libcall.
...
llvm-svn: 56028
2008-09-09 23:02:14 +00:00
53b728c27c
Fix PR2757. Ignore liveinterval register allocation preference if the preference register is not in the right register class. This can happen due to sub-register coalescing.
...
llvm-svn: 56006
2008-09-09 20:22:01 +00:00
1e97901388
Fix a constant lowering bug. Now we can do load and store instructions with funky getelementptr embedded in the address operand.
...
llvm-svn: 55975
2008-09-09 01:26:59 +00:00
ab4928a6e5
Reapply 55902: Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets
...
llvm-svn: 55960
2008-09-08 21:14:36 +00:00
35883b7eec
Reapply 55903: Testcase for 64-bit lowering of eh_return & unwind_init
...
llvm-svn: 55959
2008-09-08 21:14:19 +00:00
554e6898ff
Add a target triple; apparently LLVM doesn't use 64-bit
...
data directives on darwin.
llvm-svn: 55941
2008-09-08 20:16:18 +00:00
6da384d980
Remove these testcases associated with changes between r 55898 and r 55909.
...
llvm-svn: 55931
2008-09-08 18:00:39 +00:00
99b83712f3
Reverting r55898 to r55909. One of these patches was causing an ICE during the full bootstrap on Darwin:
...
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_negdi2 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_negdi2_s.o
Assertion failed: (TargetRegisterInfo::isVirtualRegister(regA) &&
TargetRegisterInfo::isVirtualRegister(regB) && "cannot update physical
register live information"), function runOnMachineFunction, file
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/TwoAddressInstructionPass.cpp,
line 311.
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/bin/
-B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/lib/
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/include
-isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.4.0/sys-include
-O2 -O2 -g -O2 -DIN_GCC -W -Wall -Wwrite-strings
-Wstrict-prototypes -Wmissing-prototypes -Wold-style-definition
-isystem ./include -fPIC -pipe -g -DHAVE_GTHR_DEFAULT -DIN_LIBGCC2
-D__GCC_FLOAT_NOT_NEEDED -I. -I. -I../../llvm-gcc.src/gcc
-I../../llvm-gcc.src/gcc/. -I../../llvm-gcc.src/gcc/../include
-I./../intl -I../../llvm-gcc.src/gcc/../libcpp/include
-I../../llvm-gcc.src/gcc/../libdecnumber -I../libdecnumber
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.obj/include
-I/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/include
-DSHARED -m64 -DL_lshrdi3 -c ../../llvm-gcc.src/gcc/libgcc2.c -o
libgcc/x86_64/_lshrdi3_s.o
../../llvm-gcc.src/gcc/unwind-dw2.c:1527: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
{standard input}:unknown:Undefined local symbol LBB21_11
{standard input}:unknown:Undefined local symbol LBB21_12
{standard input}:unknown:Undefined local symbol LBB21_13
{standard input}:unknown:Undefined local symbol LBB21_8
llvm-svn: 55928
2008-09-08 17:59:12 +00:00
d172048b59
Handle calls which produce i1 results: promote to i8 but and it with 1 to get the low bit.
...
llvm-svn: 55925
2008-09-08 17:15:42 +00:00
f9b2054df1
Add AsmPrinter support for i128 and larger static initializer data.
...
llvm-svn: 55919
2008-09-08 16:40:13 +00:00
f5e48008a4
Testcase for 64-bit lowering of eh_return & unwind_init
...
llvm-svn: 55903
2008-09-08 14:23:16 +00:00
f0d1a0ccf0
Add test for checking proper lowering of eh_return & unwind init intrinsics on 32bit x86 targets
...
llvm-svn: 55902
2008-09-08 14:22:57 +00:00
d3ca8be4a9
Add testcase from bug 2770.
...
llvm-svn: 55897
2008-09-08 11:17:54 +00:00
ca14c07175
Correctly handle physical register inputs. They are not explicit input operands in the resulting machine instrs.
...
llvm-svn: 55893
2008-09-08 08:39:33 +00:00
b928669409
Handle x86 truncate to i8 with target hook for now.
...
llvm-svn: 55877
2008-09-07 08:47:42 +00:00
a9c52c8219
Fix for PR2687: Add patterns to match sint_to_fp and fp_to_sint for <2 x
...
i32>. This is a little messy, but it works.
We should really get rid of the intrinsics, though, since they map
perfectly well to standard LLVM instructions.
llvm-svn: 55864
2008-09-05 23:07:03 +00:00
d4e01dce74
Fix test.
...
llvm-svn: 55849
2008-09-05 20:04:37 +00:00
4f0d21592a
If SSE2 is available, x86 should pass first 3 f32/f64 arguments in XMM registers for fastcc calls.
...
llvm-svn: 55840
2008-09-05 17:24:07 +00:00
6c94b99c62
For whatever the reason, x86 CallingConv::Fast (i.e. fastcc) was not passing scalar arguments in registers. This patch defines a new fastcc CC which is slightly different from the FastCall CC. In addition to passing integer arguments in ECX and EDX, it also specify doubles are passed in 8-byte slots which are 8-byte aligned (instead of 4-byte aligned). This avoids a potential performance hazard where doubles span cacheline boundaries.
...
llvm-svn: 55807
2008-09-04 22:59:58 +00:00
b8c7ba228f
Fix the ordering of operands to the store (inverted relative to LLVM IR), and fix the testcase.
...
llvm-svn: 55777
2008-09-04 16:48:33 +00:00
4f948bd87a
Add a first attempt at implementing stores for X86 fast isel using target hooks.
...
Dan or Evan, please review.
llvm-svn: 55764
2008-09-04 07:08:58 +00:00
8d8f47d50b
Load from GV stub should be locally CSE'd.
...
llvm-svn: 55763
2008-09-04 06:18:33 +00:00
3152edf474
Remove code that pad number of bytes to pop for X86_FastCall CC. The code doesn't do the "aligning" for Cygwin, Mingw, and Windows. But aligning it on Darwin and Linux breaks gcc compatibility. That ruled out all the platforms we support!
...
llvm-svn: 55756
2008-09-04 01:04:15 +00:00
a41ee2974b
Add X86 target hook to implement load (even from GlobalAddress).
...
llvm-svn: 55693
2008-09-03 06:44:39 +00:00
fdbe925974
Turn this legalize types test on.
...
llvm-svn: 55605
2008-09-01 12:00:55 +00:00
aebd2662d3
Revert the "XFAIL" for the rotate_ops.ll testcase. Instead, mark ISD::ROTR
...
instructions in CellSPU as "Expand" so that they won't be generated. I added a
"FIXME" so that this hack can be addressed and reverted once ISD::ROTR is
supported in the .td files.
llvm-svn: 55582
2008-08-31 02:59:23 +00:00
91bf1e0dc5
CellSPU doesn't appear to support fully the "ISD::ROTR" operation. The DAG
...
combiner can now generate ROTR if the backend says that it can handle it. Cell
SPU says this, but gets an error from code gen saying that it can't select
ROTR. I'm xfailing this test until this can be fixed.
llvm-svn: 55579
2008-08-31 02:32:12 +00:00
a3771d5bd9
Re-apply 55467 with fix. If copy is being replaced by remat'ed def, transfer the implicit defs onto the remat'ed instruction.
...
llvm-svn: 55564
2008-08-30 09:09:33 +00:00
cfb7f3abdf
Transform (x << (y&31)) -> (x << y). This takes advantage of the fact x86 shift instructions 2nd operand (shift count) is limited to 0 to 31 (or 63 in the x86-64 case).
...
llvm-svn: 55558
2008-08-30 02:03:58 +00:00
35c2abf4c2
Testcases for ppc atomics.
...
llvm-svn: 55556
2008-08-30 00:54:31 +00:00
3fddc7e906
Swap fp comparison operands and change predicate to allow load folding (safely this time).
...
llvm-svn: 55553
2008-08-29 23:22:12 +00:00
0b82607fa1
xfail this.
...
llvm-svn: 55550
2008-08-29 22:59:13 +00:00
9fc9d2ec3b
allow this to pass.
...
llvm-svn: 55540
2008-08-29 17:18:26 +00:00
960b17a3c2
Swap fp comparison operands and change predicate to allow load folding.
...
llvm-svn: 55521
2008-08-28 23:48:31 +00:00
1e137300bd
In lowering SELECT_CC, removed cases where we can't flip the true and false when the compare value has a NaN
...
llvm-svn: 55499
2008-08-28 21:04:05 +00:00
f27e33baa7
Optimize DAGCombiner's worklist processing. Previously it started
...
its work by putting all nodes in the worklist, requiring a big
dynamic allocation. Now, DAGCombiner just iterates over the AllNodes
list and maintains a worklist for nodes that are newly created or
need to be revisited. This allows the worklist to stay small in most
cases, so it can be a SmallVector.
This has the side effect of making DAGCombine not miss a folding
opportunity in alloca-align-rounding.ll.
llvm-svn: 55498
2008-08-28 21:01:56 +00:00
04cf2e4540
Revert r55467; it causes regressions in UnitTests/Vector/divides,
...
Benchmarks/sim/sim, and others on x86-64.
llvm-svn: 55475
2008-08-28 17:22:54 +00:00
6975602024
If a copy isn't coalesced, but its src is defined by trivial computation. Re-materialize the src to replace the copy.
...
llvm-svn: 55467
2008-08-28 07:53:51 +00:00
897b2380d8
This test crashes on non-x86 host; make SSE explicit.
...
Feel free to fix a better way!
llvm-svn: 55456
2008-08-28 01:51:09 +00:00
5ca269e684
Basic FastISel support for floating-point constants.
...
llvm-svn: 55401
2008-08-27 01:09:54 +00:00
09f8cef571
If an xmm register is referenced explicitly in an inline asm, make sure to
...
assign it to a version of the xmm register with the regclass that matches its
type. This fixes PR2715, a bug handling some crazy xpcom case in mozilla.
llvm-svn: 55358
2008-08-26 06:19:02 +00:00
f00f1e50b5
Try approach to moving call address load inside of callseq_start. Now it's done during the preprocess of x86 isel. callseq_start's chain is changed to load's chain node; while load's chain is the last of callseq_start or the loads or copytoreg nodes inserted to move arguments to the right spot.
...
llvm-svn: 55338
2008-08-25 21:27:18 +00:00
32635dbfb2
Add support for fast isel of (integer) immediate materialization pattens, and use them to support
...
bitcast of constants in fast isel.
llvm-svn: 55325
2008-08-25 20:20:32 +00:00
17d5be2d0a
Adjust grep's for new code sequence.
...
llvm-svn: 55320
2008-08-25 18:53:58 +00:00
e414681352
Fix asm printing of MOVSDto64mr and MOV64toSDrm.
...
llvm-svn: 55300
2008-08-25 04:11:42 +00:00
934b374bc8
Fix this test. Don't null out the file, just XFAIL it until patch can be fixed.
...
llvm-svn: 55296
2008-08-24 21:48:46 +00:00
5b836c5f77
Temporarily reverting r55292. It's causing a bootstraping failure:
...
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc ... src/libiberty/make-temp-file.c -o make-temp-file.o
Assertion failed: (Node2Index[SU->NodeNum] > Node2Index[I->Dep->NodeNum] && "Wrong topological sorting"), function InitDAGTopologicalSorting, file /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm.src/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp, line 508.
../../../../llvm-gcc.src/libiberty/hashtab.c:955: internal compiler error: Abort trap
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://developer.apple.com/bugreporter > for instructions.
make[4]: *** [hashtab.o] Error 1
make[4]: *** Waiting for unfinished jobs....
make[3]: *** [multi-do] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libiberty] Error 2
make: *** [all] Error 2
llvm-svn: 55295
2008-08-24 21:45:30 +00:00
8fa17424f7
Move callseq_start above the call address load to allow load to be folded into the call node.
...
llvm-svn: 55292
2008-08-24 19:19:55 +00:00
55e9d7c178
Testcase for 64bit maskmovq
...
llvm-svn: 55239
2008-08-23 15:53:47 +00:00
bb170bd08c
Test all currently supported atomic builtins on x86-{32,64}.
...
These just test that they go through the BE.
llvm-svn: 55208
2008-08-22 22:39:21 +00:00
49e19e906f
Factor out the predicate check code from DAGISelEmitter.cpp
...
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.
llvm-svn: 55156
2008-08-22 00:20:26 +00:00
1a6e930ea4
Testcase for PR2585.
...
llvm-svn: 55151
2008-08-21 23:04:49 +00:00
46989c637d
Add -mattr=sse2 so this test doesn't fail on non-x86 hosts.
...
llvm-svn: 55145
2008-08-21 22:34:25 +00:00
c360f3ba50
Make x86 and sse2 explicit for non-x86 hosts.
...
llvm-svn: 55141
2008-08-21 21:26:06 +00:00
9534ea03e8
Fix a number of byval / memcpy / memset related codegen issues.
...
1. x86-64 byval alignment should be max of 8 and alignment of type. Previously the code was not doing what the commit message was saying.
2. Do not use byte repeat move and store operations. These are slow.
llvm-svn: 55139
2008-08-21 21:00:15 +00:00
cdf1a276e3
getelementptr doesn't work on x86-64 yet, because it
...
has MOV64ri32 and no plain MOV64ri.
llvm-svn: 55126
2008-08-21 17:28:42 +00:00
efb7d2d03d
MVT::getMVT uses iPTR for pointer types, while we need the actual
...
intptr_t type in this case. FastISel can now select simple
getelementptr instructions.
llvm-svn: 55125
2008-08-21 17:25:26 +00:00
fe9056584b
Basic fast-isel support for instructions with constant int operands.
...
llvm-svn: 55099
2008-08-21 01:41:07 +00:00
eaef5f612a
Add a -march line for this test, and run it on x86-64 too for fun.
...
llvm-svn: 55030
2008-08-20 00:56:07 +00:00
b16a7783c5
Add FastISel support for floating-point operations.
...
llvm-svn: 55021
2008-08-20 00:23:20 +00:00
a3e4d5a5e1
Add FastISel support for several more binary operators.
...
llvm-svn: 55020
2008-08-20 00:11:48 +00:00
e79740851f
Add support for the __sync_sub_and_fetch atomics and friends for X86. The code
...
was already present, but not hooked up to anything.
llvm-svn: 55018
2008-08-19 23:09:18 +00:00
065e24709e
Fast-isel is now *minimally* functional. Add a testcase to
...
demonstrate the extent of its capabilities. Note that it
only attempts to operate on one of the blocks in this
testcase.
llvm-svn: 55016
2008-08-19 22:37:59 +00:00
5afbf510aa
Add support for 8 and 16 bit forms of __sync
...
builtins on X86.
Change "lock" instructions to be on a separate line.
This is needed to work around a bug in the Darwin
assembler.
llvm-svn: 54999
2008-08-19 18:47:28 +00:00
ab35bfdf18
Fix a (u)comiss intrinsic lowering bug. It was using anyext which can return junk in higher bits. Patch by Nate Begeman.
...
llvm-svn: 54903
2008-08-17 19:22:34 +00:00
550c9af91f
Improve support for vector casts in LLVM IR and CodeGen.
...
llvm-svn: 54784
2008-08-14 20:04:46 +00:00
7e3c392248
Allow SelectionDAG to create EXTRACT_VECTOR_ELT nodes with
...
non-constant indices. Only a few of the peephole checks require
a constant index.
llvm-svn: 54764
2008-08-13 21:51:37 +00:00
c82ad79c64
Improve the grep commands for this test to be tolerant of ABI
...
differences, and to be more specific.
llvm-svn: 54648
2008-08-11 20:10:41 +00:00
127bb03b8c
Take the FrameOffset into account when computing the alignment
...
of stack objects. This fixes PR2656.
llvm-svn: 54646
2008-08-11 18:27:03 +00:00
4e2f3ace2c
Add an EXTRACTPSmr pattern to match the pattern that
...
X86ISelLowering creates.
llvm-svn: 54544
2008-08-08 18:30:21 +00:00
655fa0fec4
It's not legal to output a GV in a coalesced section if it's used in an ARM PIC relative constantpool.
...
llvm-svn: 54519
2008-08-08 06:56:16 +00:00
42a19b6933
Don't crash printing the asm for a ConstantExpr PtrToInt just because the int
...
is narrower than the pointer. This testcase emits:
.byte (((17) - 16) & 255)
llvm-svn: 54517
2008-08-08 06:34:07 +00:00
93da7e6924
Support added for ctlz intrinsic, test case added.
...
llvm-svn: 54516
2008-08-08 06:16:31 +00:00
6067b44985
[Last] Batch 7 of Mips CodeGen tests
...
llvm-svn: 54512
2008-08-08 04:12:42 +00:00
b60eebbab8
Batch 6 of Mips CodeGen tests
...
llvm-svn: 54511
2008-08-08 04:11:30 +00:00
9c8b9d4606
Batch 5 of Mips CodeGen tests
...
llvm-svn: 54510
2008-08-08 04:09:57 +00:00
32d4b5a44e
Batch 4 of Mips CodeGen tests
...
llvm-svn: 54509
2008-08-08 04:08:30 +00:00
118a9e4813
Batch 3 of Mips CodeGen tests
...
llvm-svn: 54508
2008-08-08 04:05:51 +00:00
6b9077a5e4
Batch 2 of Mips CodeGen tests
...
llvm-svn: 54507
2008-08-08 04:03:25 +00:00
98ab9b334b
Batch 1 of Mips CodeGen tests, more coming...
...
I had a lot of simple local codegen tests and they are now ready to be placed
in test/CodeGen.
llvm-svn: 54506
2008-08-08 03:58:34 +00:00
9dbbd75068
Print section flags ok on platforms, which use '@' as comment string. Fix test.
...
llvm-svn: 54460
2008-08-07 09:55:06 +00:00
527ca7e253
Re-enable elimination of unnecessary SUBREG_TO_REG instructions in
...
LowerSubregs, and fix an x86-64 isel bug that this exposed.
SUBREG_TO_REG for x86-64 implicit zero extension is only safe for
isel to generate when the source is known to always have zeros in
the high 32 bits. The EXTRACT_SUBREG instruction does not clear
the high 32 bits.
llvm-svn: 54444
2008-08-07 02:54:50 +00:00
a8dbaeb1df
Add an extra example that shouldn't get an and instruction.
...
llvm-svn: 54443
2008-08-07 02:23:06 +00:00
91c2c432c0
Re-introduce the 8-bit subreg zext-inreg patterns for x86-32,
...
this time using MOV32to32_ and MOV16to16_. Thanks to Evan for
suggesting this.
llvm-svn: 54418
2008-08-06 18:27:21 +00:00
7823a411d5
Fix PR2620: Fix X86cmppd selection code so it expects operands to be v2f64.
...
llvm-svn: 54376
2008-08-05 22:19:15 +00:00
aa33b932bd
Fix PR2596: out of bound reference.
...
llvm-svn: 54375
2008-08-05 21:51:46 +00:00
b358c8f482
Update the remaining tests not to use -disable-correct-folding, and remove two
...
that couldn't be updated.
llvm-svn: 54359
2008-08-05 18:19:14 +00:00
8ccb8d35c4
One more -disable-correct-folding case removed.
...
llvm-svn: 54358
2008-08-05 18:08:56 +00:00
ae0af127a6
Remove another -disable-correct-folding use.
...
llvm-svn: 54357
2008-08-05 18:05:58 +00:00
31a0dea5c0
Eliminate another use of -disable-correct-folding.
...
llvm-svn: 54356
2008-08-05 18:03:01 +00:00
04c047ddca
This check is unnecessary, and getting rid of it removes a use of -disable-correct-folding.
...
llvm-svn: 54355
2008-08-05 17:52:54 +00:00
252fa16db1
Remove the need for -disable-correct-folding from this test.
...
llvm-svn: 54354
2008-08-05 17:49:52 +00:00
0ca10c9572
Fix PR2568: Fix bug that cause redudant kill marker after its live interval has been extended due to coalescing.
...
llvm-svn: 54346
2008-08-05 07:10:38 +00:00
5018bd032a
Update these tests to work by disabling the new correct CFG generation. This flag should ONLY be used to for tests like these.
...
llvm-svn: 54334
2008-08-04 23:55:29 +00:00
90c724cadc
Fix SDISel lowering of PHI nodes to use ComputeValueVTs.
...
This allows it to work correctly on aggregate values.
This fixes PR2623.
llvm-svn: 54331
2008-08-04 23:42:46 +00:00
6e023e63cd
Fix SDISel lowering of zeroinitializer and undef to use ComputeValueVTs.
...
This allows it to work correctly on nested aggregate values.
This fixes PR2625.
llvm-svn: 54330
2008-08-04 23:30:41 +00:00
962178e77e
Make sse2 explicit, for non-x86 hosts.
...
llvm-svn: 54251
2008-07-31 20:16:33 +00:00
345d63ccf2
Improve dagcombining for sext-loads and sext-in-reg nodes.
...
llvm-svn: 54239
2008-07-31 00:50:31 +00:00
2fe4352691
Don't look for leaf values to store when lowering stores of
...
empty structs. This fixes PR2612.
llvm-svn: 54226
2008-07-30 18:36:51 +00:00
f8cc0aa87d
I missed this file in r54223. movzbl is now used instead
...
of movzbw here.
llvm-svn: 54224
2008-07-30 18:23:34 +00:00
86b06335aa
Reapply r54147 with a constraint to only use the 8-bit
...
subreg form on x86-64, to avoid the problem with x86-32
having GPRs that don't have 8-bit subregs.
Also, change several 16-bit instructions to use
equivalent 32-bit instructions. These have a smaller
encoding and avoid partial-register updates.
llvm-svn: 54223
2008-07-30 18:09:17 +00:00
2c839d4b1e
Added support for overloading intrinsics (atomics) based on pointers
...
to different address spaces. This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32
llvm-svn: 54195
2008-07-30 04:36:53 +00:00
fa4120530e
Fix PR2609. If a label is deleted, then it needs
...
to be marked invalid regardless of whether it is
a debug, an exception handling or (hopefully) a
GC label.
llvm-svn: 54172
2008-07-29 20:56:02 +00:00
43105328d3
Revert 54147.
...
llvm-svn: 54148
2008-07-29 01:02:18 +00:00
26ec56c75c
Add x86 isel patterns to match what would be a ZERO_EXTEND_INREG operation,
...
which is represented in codegen as an 'and' operation. This matches them
with movz instructions, instead of leaving them to be matched by and
instructions with an immediate field.
llvm-svn: 54147
2008-07-28 22:18:25 +00:00
108c58aef4
Fix embedded CRLF characters.
...
llvm-svn: 54125
2008-07-27 18:37:58 +00:00
59063cb315
Fix test RUN line
...
llvm-svn: 54040
2008-07-25 19:08:59 +00:00
283b2da27a
Disable mov{L, LP, HP, HLP, *DUP} shuffles for mmx
...
mmx needs its own fancy shuffle logic based on unpack; for now we get correct but awful code.
Also commit Mon Ping's VSETCC patch
llvm-svn: 54039
2008-07-25 19:05:58 +00:00
4e6a25ac45
This test needs -aggressive-remat enabled.
...
llvm-svn: 54015
2008-07-25 15:25:32 +00:00
c90a11256e
Teach ARM isLegalAddressingMode to handle unknown type without crashing. This fixes pr2589.
...
llvm-svn: 54004
2008-07-25 00:55:17 +00:00
Chris Lattner