Commit Graph

22 Commits

Author SHA1 Message Date
Gabor Buella a51e0c2243 [X86] directstore and movdir64b intrinsics
Reviewers: spatel, craig.topper, RKSimon

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45984

llvm-svn: 331249
2018-05-01 10:05:42 +00:00
Gabor Buella eba6c42e66 [X86] WaitPKG intrinsics
Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45254

llvm-svn: 330463
2018-04-20 18:44:33 +00:00
Gabor Buella b220dd2b6c [X86] Introduce cldemote intrinsic
Reviewers: craig.topper, zvi

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D45257

llvm-svn: 329993
2018-04-13 07:37:24 +00:00
Gabor Buella a052016ef2 [x86] wbnoinvd intrinsic
The WBNOINVD instruction writes back all modified
cache lines in the processor’s internal cache to main memory
but does not invalidate (flush) the internal caches.

Reviewers: craig.topper, zvi, ashlykov

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D43817

llvm-svn: 329848
2018-04-11 20:09:09 +00:00
Craig Topper 260ed8647a [X86] Fix typo in cpuid.h, bit_AVX51SER->bit_AVX512ER.
llvm-svn: 326807
2018-03-06 16:06:44 +00:00
Craig Topper 54b3f718e4 [X86] Add more CPUID bits to cpuid.h to match gcc and support icelake features.
llvm-svn: 321129
2017-12-20 00:46:09 +00:00
Craig Topper b2f8b311d1 [X86] Add more feature flag bit defines to cpuid.h for gcc compatibility.
llvm-svn: 307507
2017-07-09 17:43:11 +00:00
Craig Topper f6e8408a11 [X86] Add __get_cpuid_count to cpuid.h. Update __get_cpuid to check the maximum level support before accessing the leaf. Rename level to leaf everywhere.
This matches gcc behavior.

llvm-svn: 307506
2017-07-09 17:43:10 +00:00
Dimitry Andric f8099f256d Add more gcc compatibility names to clang's cpuid.h
Summary:
Some cpuid bit defines are named slightly different from how gcc's
cpuid.h calls them.

Define a few more compatibility names to appease software built for gcc:

* `bit_PCLMUL`      alias of `bit_PCLMULQDQ`
* `bit_SSE4_1`      alias of `bit_SSE41`
* `bit_SSE4_2`      alias of `bit_SSE42`
* `bit_AES`         alias of `bit_AESNI`
* `bit_CMPXCHG8B`   alias of `bit_CX8`

While here, add the misssing 29th bit, `bit_F16C` (which is how gcc
calls this bit).

Reviewers: joerg, rsmith

Subscribers: bruno, cfe-commits

Differential Revision: https://reviews.llvm.org/D22010

llvm-svn: 277307
2016-07-31 20:23:23 +00:00
Joerg Sonnenberger 2960178a77 Fix trailing commas in AMD define.
llvm-svn: 218825
2014-10-01 21:22:17 +00:00
Joerg Sonnenberger e028e05a7e Add the various signature macros.
llvm-svn: 218824
2014-10-01 21:21:42 +00:00
Joerg Sonnenberger cf0740454d Rename bit_RDRAND to bit_RDRND to match GCC's version of this header.
llvm-svn: 218823
2014-10-01 21:21:16 +00:00
Akira Hatanaka 416efb5f90 Fix bugs in cpuid.h.
This commit makes two changes:

- Remove the push and pop instructions that were saving and restoring %ebx
  before and after cpuid in 32-bit pic mode. We were doing this to ensure we
  don't lose the GOT address in pic register %ebx, but this isn't necessary
  because the GOT address is kept in a virtual register.

- In 64-bit mode, preserve base register %rbx around cpuid.

This fixes PR20311 and rdar://problem/17686779.

llvm-svn: 218173
2014-09-20 01:31:09 +00:00
Nico Weber ef9a766555 Add bit_FXSAVE as an alias for bit_FXSR, for gcc compat.
llvm-svn: 197399
2013-12-16 17:54:57 +00:00
Roman Divacky 4dcb5dbb53 This patch implements __get_cpuid_max() as an inline and __cpuid() and
__cpuid_count() as macros to be compatible with GCC's cpuid.h.  It also adds
bit_<foo> constants for the various feature bits as described in version 039
(May 2011) of Intel's SDM Volume 2 in the description of the CPUID
instruction.  The list of bit_<foo> constants is a bit exhaustive (GCC
doesn't do near this many).  More bits could be added from a newer version of
SDM if desired.

Patch by John Baldwin!

llvm-svn: 186696
2013-07-19 17:28:36 +00:00
Richard Smith 584f7dcc0e Add tests that build modules for our builtin headers, and fix two buglets exposed by doing so.
llvm-svn: 178736
2013-04-04 02:55:24 +00:00
David Blaikie 3302f2bd46 PR14964: intrinsic headers using non-reserved identifiers
Several of the intrinsic headers were using plain non-reserved identifiers.
C++11 17.6.4.3.2 [global.names] p1 reservers names containing a double
begining with an underscore followed by an uppercase letter for any use.

I think I got them all, but open to being corrected. For the most part I
didn't bother updating function-like macro parameter names because I don't
believe they're subject to any such collission - though some function-like
macros already follow this convention (I didn't update them in part because
the churn was more significant as several function-like macros use the double
underscore prefixed version of the same name as a parameter in their
implementation)

llvm-svn: 172666
2013-01-16 23:08:36 +00:00
Douglas Gregor 4c69859b56 Make cpuid.h actually work with -std=c99 <rdar://problem/12552716>.
While we're here, extend the module map to cover most of the
newly-added instrinsic headers. Only wmmintrin.h is missing, because
it needs to be split into AES/PCLMUL subheaders (as a separate commit).

llvm-svn: 167398
2012-11-05 20:11:10 +00:00
Rafael Espindola 49118520de Fix comment.
llvm-svn: 145271
2011-11-28 20:05:27 +00:00
Rafael Espindola 0618d14edf Error on non x86 architectures.
llvm-svn: 145185
2011-11-27 15:21:33 +00:00
Rafael Espindola fd03d0b733 Fix file name in comments.
llvm-svn: 145184
2011-11-27 15:13:54 +00:00
Rafael Espindola d086573a4d Add the minimum implementation of cpuid.h. This works on "modern" intel cpus
and on clang, which seams to handled "=b" correctly even when ebx is the
PIC register.

llvm-svn: 145149
2011-11-26 20:53:19 +00:00