Commit Graph

69541 Commits

Author SHA1 Message Date
Dinesh Dwivedi f675f4201b Added instcombine for 'MIN(MIN(A, 27), 93)' and 'MAX(MAX(A, 93), 27)'
MIN(MIN(A, 23), 97) -> MIN(A, 23)
MAX(MAX(A, 97), 23) -> MAX(A, 97)

Differential Revision: http://reviews.llvm.org/D3629

llvm-svn: 208849
2014-05-15 06:13:40 +00:00
Dinesh Dwivedi 837c16097e Added inst combine transforms for single bit tests from Chris's note
if ((x & C) == 0) x |= C becomes x |= C
if ((x & C) != 0) x ^= C becomes x &= ~C
if ((x & C) == 0) x ^= C becomes x |= C
if ((x & C) != 0) x &= ~C becomes x &= ~C
if ((x & C) == 0) x &= ~C becomes nothing

Z3 Verifications code for above transform
http://rise4fun.com/Z3/Pmsh

Differential Revision: http://reviews.llvm.org/D3717

llvm-svn: 208848
2014-05-15 06:01:33 +00:00
Jonathan Roelofs 4971b40d7e Fix some dyslexia in an assert message
llvm-svn: 208842
2014-05-15 02:24:50 +00:00
Alp Toker beaca19c7c Fix typos
llvm-svn: 208839
2014-05-15 01:52:21 +00:00
Jiangning Liu 09cc564310 [ARM64] Support aggressive fastcc/tailcallopt breaking ABI by popping out argument stack from callee.
llvm-svn: 208837
2014-05-15 01:33:17 +00:00
Eric Christopher 737e089bda Move the TargetMachine MC options to MCTargetOptions. No functional
change.

llvm-svn: 208832
2014-05-15 01:08:00 +00:00
David Majnemer 186c94244c InstCombine: Optimize -x s< cst
Summary:
This gets rid of a sub instruction by moving the negation to the
constant when valid.

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3773

llvm-svn: 208827
2014-05-15 00:02:20 +00:00
David Blaikie 91e8104622 DwarfDebug: Don't set frame index locations on abstract variables.
Abstract variables should never have/use locations. In this case the
data wasn't used, so no functional change intended here, just
simplification.

llvm-svn: 208820
2014-05-14 22:51:59 +00:00
David Blaikie 9ba7254688 DebugInfo: Sure up subprogram variable list handling with more assertions and fewer conditionals.
Many old tests using prior schemas still had some brokenness here (both
indirect arrays and arrays with single bogus elements). Fixed those up
so they don't hit the new assertions.

Also reduced nesting in some places, etc.

llvm-svn: 208817
2014-05-14 21:52:46 +00:00
David Blaikie 7af6e6f267 DebugInfo: Assert that a CU's subprogram list contains only subprograms.
llvm-svn: 208816
2014-05-14 21:52:37 +00:00
Kevin Enderby e858a65323 Teach llvm-nm to know about fat archives (aka MachOUniversal files
containing archives).  First step as other tools will be updated next.

llvm-svn: 208812
2014-05-14 21:18:50 +00:00
Jay Foad a0653a3e6c Rename ComputeMaskedBits to computeKnownBits. "Masked" has been
inappropriate since it lost its Mask parameter in r154011.

llvm-svn: 208811
2014-05-14 21:14:37 +00:00
David Majnemer 2d6c023576 InstSimplify: Optimize signed icmp of -(zext V)
Summary:
We know that -(zext V) will always be <= zero, simplify signed icmps
that have these.

Uncovered using http://www.cs.utah.edu/~regehr/souper/

Reviewers: nicholas

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D3754

llvm-svn: 208809
2014-05-14 20:16:28 +00:00
David Blaikie f662f0a65e DebugInfo: Do not delay attaching DW_AT_inline attribute to abstract definitions.
This is just unneccessary - we only create abstract definitions when
we're inlining anyway, so there's no reason to delay this to see if
we're going to inline anything.

llvm-svn: 208798
2014-05-14 17:58:53 +00:00
Christian Pirker 6692e7c116 ARM-BE: test files for vector argument passing
Reviewed at http://reviews.llvm.org/D3766

llvm-svn: 208793
2014-05-14 16:59:44 +00:00
Christian Pirker 85cdab63c4 [ARM64-BE] Fix byte order of CIE and FDE frames for exception handling
Reviewed at http://reviews.llvm.org/D3741

llvm-svn: 208792
2014-05-14 16:51:58 +00:00
Logan Chien 95188b9092 Fix ARM EHABI when function has landingpad and nounwind.
If the function has the landingpad instruction, then the
handlerdata should be emitted even if the function has
nouwnind attribute.  Otherwise, following code will not
work:

    void test1() noexcept {
      try {
        throw_exception();
      } catch (...) {
        log_unexpected_exception();
      }
    }

Since the cantunwind was incorrectly emitted and the
LSDA is not available.

llvm-svn: 208791
2014-05-14 16:38:30 +00:00
Benjamin Kramer 594f963ea6 X86: If we have an instruction that sets a flag and a zero test on the input of that instruction try to eliminate the test.
For example
	tzcntl	%edi, %ebx
	testl %edi, %edi
	je	.label

can be rewritten into
	tzcntl	%edi, %ebx
	jb 	.label

A minor complication is that tzcnt sets CF instead of ZF when the input
is zero, we have to rewrite users of the flags from ZF to CF. Currently
we recognize patterns using lzcnt, tzcnt and popcnt.

Differential Revision: http://reviews.llvm.org/D3454

llvm-svn: 208788
2014-05-14 16:14:45 +00:00
Daniel Sanders a2ffa21d80 [mips][mips64r6] Add sel.s and sel.d
Summary:
Also use named constants for common opcode fields.

Depends on D3669

Reviewers: vmedic, zoran.jovanovic, jkolek

Reviewed By: jkolek

Differential Revision: http://reviews.llvm.org/D3670

llvm-svn: 208784
2014-05-14 15:29:44 +00:00
Tim Northover 5f92cf60f9 ARM64: remove unneeded InstPrinter hacks
Now that TableGen handles aliases, these are unneeded. Hopefully more will be
able to go soon.

llvm-svn: 208781
2014-05-14 14:44:18 +00:00
Evgeniy Stepanov ed31ca4bdc [asan] Fix compiler warnings.
llvm-svn: 208769
2014-05-14 10:56:19 +00:00
Evgeniy Stepanov aaf4bb2394 [asan] Set debug location in ASan function prologue.
Most importantly, it gives debug location info to the coverage callback.

This change also removes 2 cases of unnecessary setDebugLoc when IRBuilder
is created with the same debug location.

llvm-svn: 208767
2014-05-14 10:30:15 +00:00
Serge Pavlov e6de9e39a8 Fix the case when reordering shuffle and binop produces a constant.
This resolves PR19737.

llvm-svn: 208762
2014-05-14 09:05:09 +00:00
Jay Foad e48d9e8efe Update the comments for ComputeMaskedBits, which lost its Mask parameter
in r154011.

llvm-svn: 208757
2014-05-14 08:00:07 +00:00
Simon Atanasyan ae6bb33ac2 [obj2yaml] Support ELF input format in the obj2yaml tool.
The ELF header e_flags field in the MIPS related test cases handled
incorrectly. The obj2yaml prints too many flags. I will fix that in the
next patches.

The patch reviewed by Michael Spencer and Sean Silva.

llvm-svn: 208752
2014-05-14 05:07:47 +00:00
Saleem Abdulrasool 27351f2022 ARM: implement support for the UDF mnemonic
The UDF instruction is a reserved undefined instruction space.  The assembler
mnemonic was introduced with ARM ARM rev C.a.  The instruction is not predicated
and the immediate constant is ignored by the CPU.  Add support for the three
encodings for this instruction.

The changes to the invalid instruction test is due to the fact that the invalid
instructions actually overlap with the undefined instruction.  Introduction of
the new instruction results in a partial decode as an undefined sequence.  Drop
the tests as they are invalid instruction patterns anyways.

llvm-svn: 208751
2014-05-14 03:47:39 +00:00
Nick Lewycky f0cf8fa941 Optimize integral reciprocal (udiv 1, x and sdiv 1, x) to not use division. This fires exactly once in a clang bootstrap, but covers a few different results from http://www.cs.utah.edu/~regehr/souper/
llvm-svn: 208750
2014-05-14 03:03:05 +00:00
David Blaikie 9b8c8cda0d Recommit r208506: DebugInfo: Include lexical scopes in inlined subroutines.
This was reverted in r208642 due to regressions surrounding file changes
within lexical scopes causing inlining information to be lost.

The issue was in LexicalScopes::getOrCreateInlinedScope, where I was
previously testing "isLexicalBlock" which is false for
"DILexicalBlockFile" (a scope used to represent changes in the current
file name) and assuming it was then a function (breaking out of the
inlined scope path and reaching for the parent non-inlined scopes). By
inverting the condition and testing for "isSubprogram" the correct
behavior is attained.

(also found some weirdness in Clang, see r208742 when reducing this test
case - the resulting test case doesn't apply with the Clang fix, but
I've added a more realistic test case to inline-scopes.ll which does
reproduce the issue and demonstrate the fix)

llvm-svn: 208748
2014-05-14 01:08:28 +00:00
Eric Christopher 02e1804d8d Fix typo in function name.
llvm-svn: 208743
2014-05-14 00:31:15 +00:00
Matt Arsenault 4b0402e317 R600/SI: Try to fix BFE operands when moving to VALU
This was broken by r208479

llvm-svn: 208740
2014-05-13 23:45:50 +00:00
Lang Hames 890758d5b3 [RuntimeDyld] Fix handling of i386 PC-rel external relocations. This fixes
several more i386 MCJIT regression test failures.

<rdar://problem/16889891>

llvm-svn: 208735
2014-05-13 22:09:07 +00:00
Louis Gerbarg 1b91aa2cf5 Add missing line breaks to debug output in CodeGenPrepare
llvm-svn: 208731
2014-05-13 21:54:22 +00:00
Benjamin Kramer 3f085ba6d6 GVN: Fix non-determinism in map iteration.
Iterating over a DenseMaop is non-deterministic and results to unpredictable IR
output.

Based on a patch by Daniel Reynaud!

llvm-svn: 208728
2014-05-13 21:06:40 +00:00
Benjamin Kramer d97f95e2f2 GVN: rangify a couple of loops.
No functionality change.

llvm-svn: 208727
2014-05-13 21:06:36 +00:00
Eric Christopher d1309ee27d Save the optimization level the subtarget was created with in a
member variable and sink the initialization of crbits into the
subtarget feature reset code.

No functional change, but this refactor will be used in a future
commit.

llvm-svn: 208726
2014-05-13 20:49:08 +00:00
Eric Christopher addf51ddde Make the split function use StringRef::split.
llvm-svn: 208723
2014-05-13 19:55:17 +00:00
Rafael Espindola 99e05cf163 Split GlobalValue into GlobalValue and GlobalObject.
This allows code to statically accept a Function or a GlobalVariable, but
not an alias. This is already a cleanup by itself IMHO, but the main
reason for it is that it gives a lot more confidence that the refactoring to fix
the design of GlobalAlias is correct. That will be a followup patch.

llvm-svn: 208716
2014-05-13 18:45:48 +00:00
Joerg Sonnenberger 94cbb666b2 Check explicitly for EHABI and just use the default settings.
Code depends on the assembler and linker to fix things up...

llvm-svn: 208715
2014-05-13 17:58:13 +00:00
Christian Pirker 39db7ec81f ARMEB: Fix byte order of EH frame unwinding instructions, with modified test file
This commit was already commited as revision rL208689 and discussd in
phabricator revision D3704.
But the test file was crashing on OS X and windows.

I fixed the test file in the same way as in rL208340.

llvm-svn: 208711
2014-05-13 16:44:30 +00:00
Joey Gouly 12a8bf09d0 [CGP] r205941 changed the logic, so that a cast happens *before* 'Result' is
compared to 'AddrMode.BaseReg'. In the case that 'AddrMode.BaseReg' is
nullptr, 'Result' will also be nullptr, so the cast causes an assertion. We
should use dyn_cast_or_null here to check 'Result' is not null and it is an
instruction.

Bug found by Mats Petersson, and I reduced his IR to get a test case.

llvm-svn: 208705
2014-05-13 15:42:45 +00:00
Rafael Espindola 2e7eceb317 Revert "ARMEB: Fix byte order of EH frame unwinding instructions"
This reverts commit r208689.

The test was crashing on OS X and windows.

llvm-svn: 208704
2014-05-13 15:19:56 +00:00
Daniel Sanders 387fc15d2c [mips] Marked up instructions added in MIPS32r2 and tested that IAS for -mcpu=mips(2|32) does not accept them
Summary:
This required a new instruction group representing the 32-bit subset of
MIPS-3 that was available in MIPS32R2.

To limit the number of tests required, only one 32-bit and one 64-bit ISA
prior to MIPS32/MIPS64 are tested.

rdhwr has been deliberately left without an ISA annotation for now. This is
because the assembler and CodeGen disagree on when the instruction is
available. Strictly speaking, it is only available in MIPS32r2 and
MIPS64r2. However, it is emulated by a kernel trap on earlier ISA's and is
necessary for TLS so CodeGen should emit it on older ISA's too.

Depends on D3696

Reviewers: vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3697

llvm-svn: 208690
2014-05-13 11:45:36 +00:00
Christian Pirker ea3514ecdb ARMEB: Fix byte order of EH frame unwinding instructions
llvm-svn: 208689
2014-05-13 11:41:49 +00:00
Daniel Sanders 579168629e [mips] Free up two values in SubtargetFeatureFlag by folding the redundant IsGP32/IsGP64 into IsGP32bit/IsGP64bit
Summary:
We are currently very close to the 32-bit limit of the current assembler
implementation. This is because there is no way to represent an instruction
that is available in, for example, Mips3 or Mips32. We have to define a
feature bit that represents this.

This patch cleans up a pair of redundant feature bits and slightly postpones the
point we will reach the limit.

Reviewers: zoran.jovanovic, jkolek, vmedic

Reviewed By: vmedic

Differential Revision: http://reviews.llvm.org/D3703

llvm-svn: 208685
2014-05-13 11:17:46 +00:00
Artyom Skrobov 6298b347b6 [un]wrap extracted from lib/Target/Target[MachineC].cpp, lib/ExecutionEngine/ExecutionEngineBindings.cpp into include/llvm/IR/DataLayout.h
llvm-svn: 208680
2014-05-13 09:45:26 +00:00
Kevin Qin 97e5d98779 [ARM64] Fix the misleading diagnostic on bad extend amount of reg+reg addressing mode.
A vague diagnostic replaced the misleading one.
This can fix bug 19502.

llvm-svn: 208669
2014-05-13 07:35:12 +00:00
Serge Pavlov b575ee8294 Fix type of shuffle resulted from shuffle merge.
This fix resolves PR19730.

llvm-svn: 208666
2014-05-13 06:07:21 +00:00
Rafael Espindola 7e2b7567a8 Assert that we don't RAUW a Constant with a ConstantExpr that contains it.
We already had an assert for foo->RAUW(foo), but not for something like
foo->RAUW(GEP(foo)) and would go in an infinite loop trying to apply
the replacement.

llvm-svn: 208663
2014-05-13 01:23:21 +00:00
Weiming Zhao dd83691cc3 Folding into CSEL when there is ZEXT between SETCC and ADD
Normally, patterns like (add x, (setcc cc ...)) will be folded into
(csel x, x+1, not cc). However, if there is a ZEXT after SETCC, they
won't be folded. This patch recognizes the ZEXT and allows the
generation of CSINC.

This patch fixes bug 19680.

llvm-svn: 208660
2014-05-13 00:40:58 +00:00
David Blaikie 290e22872d Revert "DebugInfo: Include lexical scopes in inlined subroutines."
This reverts commit r208506.

Some inlined subroutine scopes appear to be missing with this change.
Reverting while I investigate.

llvm-svn: 208642
2014-05-12 23:53:03 +00:00