6 Commits

Author	SHA1	Message	Date
Luis Marques	3d0fbafd0b	[RISCV] Switch to the Machine Scheduler ... Most of the test changes are trivial instruction reorderings and differing register allocations, without any obvious performance impact. Differential Revision: https://reviews.llvm.org/D66973 llvm-svn: 372106	2019-09-17 11:15:35 +00:00
Luis Marques	2d550d19b3	Revert Patch from Phabricator ... This reverts r372092 (git commit e38695a025) llvm-svn: 372104	2019-09-17 10:52:09 +00:00
Luis Marques	e38695a025	Patch from Phabricator ... llvm-svn: 372092	2019-09-17 09:43:08 +00:00
Bjorn Pettersson	b0eb394417	[CodeGen] Use FSHR in DAGTypeLegalizer::ExpandIntRes_MULFIX ... Summary: Simplify the right shift of the intermediate result (given in four parts) by using funnel shift. There are some impact on lit tests, but that seems to be related to register allocation differences due to how FSHR is expanded on X86 (giving a slightly different operand order for the OR operations compared to the old code). Reviewers: leonardchan, RKSimon, spatel, lebedev.ri Reviewed By: RKSimon Subscribers: hiraditya, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, PkmX, jocewei, s.egerton, pzheng, bevinh, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D67036 llvm-svn: 370813	2019-09-03 19:35:07 +00:00
Alex Bradbury	5dabe03b41	[RISCV][NFC] Add nounwind attribute to functions missing it in test/CodeGen/RISCV ... r360897 was incomplete, must have applied an old/wip patch. This is in preparation for emitting CFI directives. llvm-svn: 361493	2019-05-23 12:43:13 +00:00
Leonard Chan	95b7abdcc5	[SelectionDAG] Expand ADD/SUBCARRY ... This patch allows for expansion of ADDCARRY and SUBCARRY when the target does not support it. Differential Revision: https://reviews.llvm.org/D61411 llvm-svn: 360303	2019-05-09 01:17:48 +00:00