Commit Graph

3709 Commits

Author SHA1 Message Date
Nicolai Haehnle 411fbbf5f3 [TableGen] more helpful error message in MapTableEmitter
Differential Revision: http://reviews.llvm.org/D17275

llvm-svn: 263148
2016-03-10 18:51:58 +00:00
Craig Topper 267bdb2094 [CodeGen] Add space-optimized EmitMergeInputChains1_2 to the DAG isel matching tables. Shaves about 5100 bytes from the X86 matcher table. NFC
llvm-svn: 262815
2016-03-07 07:29:12 +00:00
Matthias Braun 42d9ad9c5b TableGen: Accept itinerary data when checking for schedmodel completeness
llvm-svn: 262548
2016-03-03 00:04:59 +00:00
Matthias Braun a939bd07d1 TableGen: Display helpfull message for incomplete models.
llvm-svn: 262399
2016-03-01 21:36:12 +00:00
Matthias Braun 17cb57995e TableGen: Check scheduling models for completeness
TableGen checks at compiletime that for scheduling models with
"CompleteModel = 1" one of the following holds:

- Is marked with the hasNoSchedulingInfo flag
- The instruction is a subclass of Sched
- There are InstRW definitions in the scheduling model

Typical steps necessary to complete a model:

- Ensure all pseudo instructions that are expanded before machine
  scheduling (usually everything handled with EmitYYY() functions in
  XXXTargetLowering).
- If a CPU does not support some instructions mark the corresponding
  resource unsupported: "WriteRes<WriteXXX, []> { let Unsupported = 1; }".
- Add missing scheduling information.

Differential Revision: http://reviews.llvm.org/D17747

llvm-svn: 262384
2016-03-01 20:03:21 +00:00
Matthias Braun 8e0a734fc5 TableGen: Add hasNoSchedulingInfo to instructions
This introduces a new flag that indicates that a specific instruction
will never be present when the MachineScheduler runs and therefore needs
no scheduling information.

This is in preparation for an upcoming commit which checks completeness
of a scheduling model when tablegen runs.

Differential Revision: http://reviews.llvm.org/D17728

llvm-svn: 262383
2016-03-01 20:03:11 +00:00
Nikolay Haustov ea8febde04 [TableGen] AsmMatcher: Skip optional operands in the midle of instruction if it is not present
Previosy, if actual instruction have one of optional operands then other optional operands listed before this also should be presented.
For example instruction v_fract_f32 v0, v1, mul:2 have one optional operand - OMod and do not have optional operand clamp. Previously this was not allowed because clamp is listed before omod in AsmString:

string AsmString = "v_fract_f32$vdst, $src0_modifiers$clamp$omod";
Making this work required some hacks (both OMod and Clamp match classes have same PredicateMethod).

Now, if MatchInstructionImpl meets formal optional operand that is not presented in actual instruction it skips this formal operand and tries to match current actual operand with next formal.

Patch by: Sam Kolton

Review: http://reviews.llvm.org/D17568

[AMDGPU] Assembler: Check immediate types for several optional operands in predicate methods
With this change you should place optional operands in order specified by asm string:

clamp -> omod
offset -> glc -> slc -> tfe
Fixes for several tests.
Depends on D17568

Patch by: Sam Kolton

Review: http://reviews.llvm.org/D17644
llvm-svn: 262314
2016-03-01 08:34:43 +00:00
Igor Breger 45ef10f110 AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling.
Differential Revision: http://reviews.llvm.org/D17564

llvm-svn: 261862
2016-02-25 13:30:17 +00:00
Xinliang David Li b439c7a16d Fix comment
llvm-svn: 261672
2016-02-23 19:18:21 +00:00
Craig Topper f5ef3f9ce6 [X86] Remove some unused encoding checks from the disassembler table building.
llvm-svn: 261418
2016-02-20 06:20:21 +00:00
Craig Topper 802e2e741c [TableGen,X86] Add NDEBUG check to a variable initialization that's only used by asserts. NFC
llvm-svn: 261188
2016-02-18 04:54:32 +00:00
Craig Topper 8a01c41059 [TableGen,X86] Remove extra optional operand from RawFrm. RawFrm with 2 immediates is handled by RawFrmImm8/RawFrmImm16.
llvm-svn: 261187
2016-02-18 04:54:29 +00:00
Craig Topper 6615654f56 [TableGen] Fix inconsistent spacing. NFC
llvm-svn: 260935
2016-02-16 04:24:58 +00:00
Craig Topper 983be941bf [TableGen] Stop passing by reference an integer that doesn't get modified. NFC
llvm-svn: 260934
2016-02-16 04:24:56 +00:00
Craig Topper b89d189d37 [TableGen] Remove unused member variable. NFC
llvm-svn: 260933
2016-02-16 04:24:54 +00:00
Craig Topper 9cd0ff1470 [TableGen] Use range-based for loop. NFC
llvm-svn: 260928
2016-02-16 02:48:30 +00:00
Craig Topper 094bbcaf63 [TableGen] Remove constant string argument from a method that's only called once. We can just hardcode the string inside. There already other things that make the method not reusable. NFC
llvm-svn: 260840
2016-02-14 05:22:01 +00:00
Craig Topper bcdb0f2ede [TableGen] Fix comment about 64-bit type I missed when I removed the underlying type in r260808.
llvm-svn: 260830
2016-02-13 17:58:14 +00:00
Craig Topper 29c55dcbde [TableGen] Use range-based for loops. NFC
llvm-svn: 260809
2016-02-13 06:03:32 +00:00
Craig Topper 2d45c1df3d No need to make the subtarget feature bit enum a uint64_t. This was a leftover from when the feature bit enum contained masks instead of bit indices.
llvm-svn: 260808
2016-02-13 06:03:29 +00:00
Craig Topper 6e2edc4b84 [TableGen] Use range-based for loops. NFC
llvm-svn: 260502
2016-02-11 07:39:29 +00:00
Craig Topper a3ebc4f03e [TableGen] Don't call emitSourceFileHeader a second time in the middle of the output file.
llvm-svn: 260501
2016-02-11 07:39:27 +00:00
Craig Topper fc1b4d4d32 [TableGen] Whitespace cleanup in output file. NFC
llvm-svn: 260500
2016-02-11 07:39:25 +00:00
Craig Topper e16efd954b [TableGen] Simplify code slightly. NFC
llvm-svn: 260499
2016-02-11 07:39:22 +00:00
Matt Arsenault f6d32496c5 SelectionDAG: Make Properties a field of SDPatternOperator
Currently you can't specify node properties like commutativity on
a PatFrag. If you want to create a PatFrag on a commutative node
with a hasOneUse predicate, this enables you to specify that the
PatFrag is also commutable.

llvm-svn: 260404
2016-02-10 18:40:04 +00:00
Tom Stellard b9f235e5ce TableGen: Add IsOptional field to AsmOperandClass
Summary:
This makes it possible to specify some operands as optional to the AsmMatcher.
Setting this field to true will prevent the AsmMatcher from emitting
'too few operands' errors when there are missing optional operands.

Reviewers: olista01, ab

Subscribers: nhaustov, arsenm, llvm-commits

Differential Revision: http://reviews.llvm.org/D15755

llvm-svn: 259913
2016-02-05 19:59:33 +00:00
David L Kreitzer f24d409dce Unify the target opcode enum in TargetOpcodes.h and the FixedInstrs array in
CodeGenTarget.cpp to avoid the ordering dependence. NFCI.

Differential Revision: http://reviews.llvm.org/D16826

llvm-svn: 259726
2016-02-03 23:17:32 +00:00
Reid Kleckner 45b6159ed3 Minor performance tweaks to llvm-tblgen (and a few that might be a good idea)
Summary:
This patch adds a reserve call to an expensive function
(`llvm::LoadIntrinsics`), and may fix a few other low hanging
performance fruit (I've put them in comments for now, so we can
discuss).

**Motivation:**

As I'm sure other developers do, when I build LLVM, I build the entire
project with the same config (`Debug`, `MinSizeRel`, `Release`, or
`RelWithDebInfo`). However, the `Debug` config also builds llvm-tblgen
in `Debug` mode. Later build steps that run llvm-tblgen then can
actually be the slowest steps in the entire build. Nobody likes slow
builds.

Reviewers: rnk, dblaikie

Differential Revision: http://reviews.llvm.org/D16832

Patch by Alexander G. Riccio

llvm-svn: 259683
2016-02-03 19:34:28 +00:00
Dylan McKay bff960a926 [TableGen] Add 'register alternative name matching' support
Summary:
This adds a new attribute which targets can set in TableGen which causes a function to be generated which matches register alternative names. This is very similar to `ShouldEmitMatchRegisterName`, except it works on alt names.

This patch is currently used by the out of tree part of the AVR backend. It reduces code duplication greatly, and has the effect that you do not need to hardcode altname to register mappings in C++.

It will not work on targets which have registers which share the same aliases.

Reviewers: stoklund, arsenm, dsanders, hfinkel, vkalintiris

Subscribers: hfinkel, dylanmckay, llvm-commits

Differential Revision: http://reviews.llvm.org/D16312

llvm-svn: 259636
2016-02-03 10:30:16 +00:00
Eugene Zelenko ecefe5a81f Fix Clang-tidy readability-redundant-control-flow warnings; other minor fixes.
Differential revision: http://reviews.llvm.org/D16793

llvm-svn: 259539
2016-02-02 18:20:45 +00:00
Craig Topper 28851b62cc [TableGen] Store result of getInstructionsByEnumValue in an ArrayRef instead of accidentally copying to a vector.
llvm-svn: 259336
2016-02-01 01:33:42 +00:00
Craig Topper 429093a9a4 No need to use utostr/utohexstr when writing into a raw_ostream. NFC
llvm-svn: 259314
2016-01-31 01:55:15 +00:00
Reid Kleckner 5b4637141e [llvm-tblgen] Avoid StringMatcher for GCC and MS builtin names
This brings the compile time of Function.cpp from ~40s down to ~4s for
me locally. It also shaves off about 400KB of object file size in a
release+asserts build.

I also realized that the AMDGPU backend does not have any GCC builtin
names to match, so the extra lookup was a no-op. I removed it to silence
a zero-length string table array warning. There should be no functional
change here.

This change really ends the story of PR11951.

llvm-svn: 258897
2016-01-27 01:43:12 +00:00
Reid Kleckner 1c93b4cd7b [llvm-tblgen] Stop emitting the intrinsic name matching code
The AMDGPU backend was the last user of the old StringMatcher
recognition code. Move it over to the new lookupLLVMIntrinsicName
funciton, which is now improved to handle all of the interesting edge
cases exposed by AMDGPU intrinsic names.

llvm-svn: 258875
2016-01-26 23:01:21 +00:00
Chris Bieneman e49730d4ba Remove autoconf support
Summary:
This patch is provided in preparation for removing autoconf on 1/26. The proposal to remove autoconf on 1/26 was discussed on the llvm-dev thread here: http://lists.llvm.org/pipermail/llvm-dev/2016-January/093875.html

"I felt a great disturbance in the [build system], as if millions of [makefiles] suddenly cried out in terror and were suddenly silenced. I fear something [amazing] has happened."
- Obi Wan Kenobi

Reviewers: chandlerc, grosbach, bob.wilson, tstellarAMD, echristo, whitequark

Subscribers: chfast, simoncook, emaste, jholewinski, tberghammer, jfb, danalbert, srhines, arsenm, dschuff, jyknight, dsanders, joker.eph, llvm-commits

Differential Revision: http://reviews.llvm.org/D16471

llvm-svn: 258861
2016-01-26 21:29:08 +00:00
Eugene Zelenko 6ac3f739ca Fix Clang-tidy modernize-use-nullptr and modernize-use-override warnings; other minor fixes.
Differential revision: reviews.llvm.org/D16568

llvm-svn: 258831
2016-01-26 18:48:36 +00:00
Reid Kleckner 86ff2689a5 Sort intrinsics by LLVM intrinsic name, rather than tablegen def name
Step one towards using a simple binary search to lookup intrinsic IDs
instead of our crazy table generated switch+memcmp+startswith code that
makes Function.cpp take about a minute to compile.  See PR24785 and
PR11951 for why we should do this.

The X86 backend contains tables that need to be sorted on intrinsic ID,
so reorder those.

llvm-svn: 258757
2016-01-26 00:55:00 +00:00
Oliver Stannard 7772f023b5 [TableGen] Fix sort order of asm operand classes
This is a fix for https://llvm.org/bugs/show_bug.cgi?id=22796.

The previous implementation of ClassInfo::operator< allowed cycles of classes
such that x < y < z < x, meaning that a list of them cannot be correctly
sorted, and the sort order could differ with different standard libraries.

The original implementation sorted classes by ValueName if they were otherwise
equal. This isn't strictly necessary, but some backends seem to accidentally
rely on it. If I reverse this comparison I get 8 test failures spread across
the AArch64, Mips and X86 backends, so I have left it in until those backends
can be fixed.

There was one case in the X86 backend where the observable behaviour of the
assembler is changed by this patch. This was because some of the memory asm
operands were not marked as children of X86MemAsmOperand.

Differential Revision: http://reviews.llvm.org/D16141

llvm-svn: 258677
2016-01-25 10:20:19 +00:00
Craig Topper 5dd7a2cc24 [TableGen] In AsmWriterEmitter unique command search, rather than storing a mapping from instruction to unique command, instead store a list of which instructions each unique command corresponds to.
This simplifies the complexity of the code that tries to find further operands to merge into the unique command.

llvm-svn: 258656
2016-01-24 07:13:28 +00:00
Craig Topper 674d238bcc [TableGen] Make a class member local to the function that populates it and consumes it later. NFC
llvm-svn: 258490
2016-01-22 05:59:43 +00:00
Craig Topper 6664c18518 [TableGen] Reorder fields in AsmWriterOperand to remove padding and reduce size. NFC
llvm-svn: 258489
2016-01-22 05:59:40 +00:00
Craig Topper db75cc184a [TableGen] Remove the CGIOpNo from AsmWriterOperand as its not used for anything. NFC
llvm-svn: 258488
2016-01-22 05:59:37 +00:00
Quentin Colombet 2d7fa7065f [GlobalISel] Add a generic machine opcode for ADD.
The selection process being split into separate passes, we need generic opcodes
to translate the LLVM IR to target independent code.

This patch adds an opcode for addition: G_ADD.

Differential Revision: http://reviews.llvm.org/D15472

llvm-svn: 258333
2016-01-20 19:14:55 +00:00
Craig Topper 0e41d0b963 [TableGen] Merge the SuperClass Record and SMRange vector into a single vector. This removes the state needed to manage the extra vector thus reducing the size of the Record class. NFC
llvm-svn: 258065
2016-01-18 19:52:37 +00:00
Craig Topper 83421eccde [TableGen] Keep a returned const reference instead of making a copy. NFC
llvm-svn: 258020
2016-01-17 20:38:21 +00:00
Craig Topper 8cc904d65b [TableGen] Replace instructions() with getInstructionsByEnumValue(). No need to make an iterator_range when we already have a function that returns an ArrayRef. NFC
llvm-svn: 258019
2016-01-17 20:38:18 +00:00
Craig Topper f926532c71 [TableGen] Return ArrayRef instead of a std::vector reference from getInstructionsByEnumValue(). NFC
llvm-svn: 258018
2016-01-17 20:38:14 +00:00
Craig Topper a15226ea51 [TableGen] Use std::find instead of a manual loop. NFC
llvm-svn: 258017
2016-01-17 19:51:14 +00:00
Craig Topper e8453b0d88 [TableGen] Use a StringRef instead of creating a new std::string. It gets passed to a function that takes a StringRef anyway. NFC
llvm-svn: 258007
2016-01-17 08:47:02 +00:00
Craig Topper 9e9ae60b9d [TableGen] Changes to AsmWriterEmitter to remove the CodeGenInstruction to AsmWriterInst map. NFC
Adds the corresponding CodeGenInstruction number to each AsmWriterInst. Then write all the operand uniqueing loops using the AsmWriterInst array and indices. Then use the CodeGenInstruction index to fill out the OpCodeInfo array.

llvm-svn: 258005
2016-01-17 08:05:33 +00:00