Commit Graph

278574 Commits

Author SHA1 Message Date
Simon Pilgrim e8715025f5 [X86] Add CMP/TEST schedule tests
llvm-svn: 320402
2017-12-11 18:32:59 +00:00
Zhihao Yuan 00c9dfdfd0 P0620 follow-up: deducing `auto` from braced-init-list in new expr
Summary:
This is a side-effect brought in by p0620r0, which allows other placeholder types (derived from `auto` and `decltype(auto)`) to be usable in a `new` expression with a single-clause //braced-init-list// as its initializer (8.3.4 [expr.new]/2).  N3922 defined its semantics.

References:
 http://wg21.link/p0620r0
 http://wg21.link/n3922

Reviewers: rsmith, aaron.ballman

Reviewed By: rsmith

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D39451

llvm-svn: 320401
2017-12-11 18:29:54 +00:00
Simon Pilgrim 5512525c5d [X86] Add AND/OR/XOR schedule tests
llvm-svn: 320400
2017-12-11 18:23:24 +00:00
Jonas Devlieghere ba915897da [dwarfdump] Fix off-by-one bug in accelerator table extractor.
This fixes a bug where the verifier was complaining about empty
accelerator tables. When the table is empty, its size is not a valid
offset as it points after the end of the section.

This patch also makes the extractor return llvm:Error instead of bool
for better error reporting in the verifier.

Differential revision: https://reviews.llvm.org/D41063

rdar://35932007

llvm-svn: 320399
2017-12-11 18:22:47 +00:00
Erich Keane 6c4835978a Revert 320391: Certain targets are failing, pulling back to diagnose.
llvm-svn: 320398
2017-12-11 18:14:51 +00:00
Simon Pilgrim 9b2a5e1e0b [X86] Add ADD/SUB schedule tests
llvm-svn: 320397
2017-12-11 18:13:40 +00:00
Malcolm Parsons d900a0c4e2 [Sema] Fix crash in unused-lambda-capture warning for VLAs
Summary:
Clang was crashing when diagnosing an unused-lambda-capture for a VLA because
From.getVariable() is null for the capture of a VLA bound.
Warning about the VLA bound capture is not helpful, so only warn for the VLA
itself.

Fixes: PR35555

Reviewers: aaron.ballman, dim, rsmith

Reviewed By: aaron.ballman, dim

Subscribers: cfe-commits

Differential Revision: https://reviews.llvm.org/D41016

llvm-svn: 320396
2017-12-11 18:00:36 +00:00
Simon Pilgrim dbe6c45fcd [X86] Add ADC/SBB schedule tests
llvm-svn: 320395
2017-12-11 17:59:05 +00:00
Rui Ueyama 8cbb3b56b9 Sort.
llvm-svn: 320394
2017-12-11 17:52:43 +00:00
Rui Ueyama 909d123893 Change function type more LLVM-ish.
Also fix variable naming style.

llvm-svn: 320393
2017-12-11 17:52:28 +00:00
Simon Pilgrim 8c2d90a2f4 [X86] Add MOVSLQ schedule tests
llvm-svn: 320392
2017-12-11 17:37:08 +00:00
Erich Keane bb322555af For Linux/gnu compatibility, preinclude <stdc-predef.h> if the file is available
As reported in llvm bugzilla 32377.
Here’s a patch to add preinclude of stdc-predef.h.

The gcc documentation says “On GNU/Linux, <stdc-predef.h> is pre-included.” See https://gcc.gnu.org/gcc-4.8/porting_to.html;

The preinclude is inhibited with –ffreestanding.

Basically I fixed the failing test cases by adding –ffreestanding which inhibits this behavior.

I fixed all the failing tests, including some in extra/test, there's a separate patch for that which is linked here

Note: this is a recommit after a test failure took down the original (r318669)

Patch By: mibintc
Differential Revision: https://reviews.llvm.org/D34158

llvm-svn: 320391
2017-12-11 17:36:42 +00:00
Rafael Espindola 63fcc5cccc Create reserved symbols early so they can be versioned.
This fixes pr35570.

We were creating these symbols after parsing version scripts, so they
could not be versioned.

We cannot move the version script parsing later because we need it for
lto.

One option is to move both addReservedSymbols and
createSyntheticSections earlier. The disadvantage is that some
sections created by createSyntheticSections replace other input
sections. For example, gdb index replaces .debug_gnu_pubnames, so it
wants to run after gc sections so that it can set S->Live to false.

What this patch does instead is to move just the ElfHeader creation
early.

llvm-svn: 320390
2017-12-11 17:23:28 +00:00
Simon Pilgrim 6d89f407db Normalize line endings. NFCI.
llvm-svn: 320389
2017-12-11 17:01:21 +00:00
Amara Emerson df9b529d42 [GlobalISel] Disable GISel for big endian.
This is due to PR26161 needing to be resolved before we can fix
big endian bugs like PR35359. The work to split aggregates into smaller LLTs
instead of using one large scalar will take some time, so in the mean time
we'll fall back to SDAG.

Some ARM BE tests xfailed for now as a result.

Differential Revision: https://reviews.llvm.org/D40789

llvm-svn: 320388
2017-12-11 16:58:29 +00:00
Simon Pilgrim fabe354b42 [X86] Add LWP schedule tests
Tag LWP instructions as WriteSystem

llvm-svn: 320387
2017-12-11 16:47:21 +00:00
Simon Pilgrim 67644be692 [X86] Add INT/INTO schedule tests
llvm-svn: 320386
2017-12-11 16:32:58 +00:00
Simon Pilgrim 1fe82016a2 [X86] Add IN/OUT schedule tests
llvm-svn: 320385
2017-12-11 16:16:40 +00:00
Simon Pilgrim d0ce975528 [X86] Add IDIV schedule tests
llvm-svn: 320384
2017-12-11 16:08:21 +00:00
Simon Pilgrim 6c29962f2e [X86] Add CMPXCHG schedule tests
llvm-svn: 320383
2017-12-11 16:04:08 +00:00
Simon Pilgrim 1c83cd18ae [X86] Add CLZERO schedule test
llvm-svn: 320382
2017-12-11 15:53:12 +00:00
Alexander Potapenko 3c934e4864 [MSan] Hotfix compilation
For some reason the override directives got removed in r320373.
I suspect this to be an unwanted effect of clang-format.

llvm-svn: 320381
2017-12-11 15:48:56 +00:00
Simon Pilgrim d9d37f8c3c [X86] Add ADCX/ADOX/XADD/XLAT schedule tests
llvm-svn: 320380
2017-12-11 15:41:52 +00:00
Nirav Dave e830b758b8 [X86] Modify Nontemporal tests to avoid deadstore optimization.
llvm-svn: 320379
2017-12-11 15:35:40 +00:00
Tony Tye 31105cc997 [AMDGPU] Rename Bonaire target to be gfx704; update target feature handling
- Rename Bonaire target to be gfx704.
- Eliminate gfx800 and make Iceland and Tonga both use gfx802 as they use the same code.
- List target features supported by each processor in the processor table together with the default value.
- Add xnack flag to e_flags.
- Remove xnack from kernel metadata and kernel descriptor since it is now a whole code object property.

Differential Revision: https://reviews.llvm.org/D40051

llvm-svn: 320378
2017-12-11 15:35:27 +00:00
Pavel Labath e0b61e3c9a dotest.py: Correctly annotate lldbinline tests with debug info categories
This enables one to run all dwo tests with dotest.py --category dwo, or
skip them with --skip-category.

llvm-svn: 320377
2017-12-11 15:28:21 +00:00
Simon Pilgrim 4f2c415a13 [X86] Add SETCC/STC/STD/UD2 schedule tests
llvm-svn: 320376
2017-12-11 15:25:31 +00:00
Dmitry Preobrazhensky ac2b02643b [AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma
See bugs 35494 and 35559:
https://bugs.llvm.org/show_bug.cgi?id=35494
https://bugs.llvm.org/show_bug.cgi?id=35559

Reviewers: vpykhtin, artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D41007

llvm-svn: 320375
2017-12-11 15:23:20 +00:00
Sanjay Patel f3436d7dab [DAGCombiner] protect against an infinite loop between shl <--> mul (PR35579)
At first, I tried to thread the x86 needle and use a target hook (isVectorShiftByScalarCheap())
to disable the transform only for non-splat pow-of-2 constants, but not AVX2, but only some
element types, but...it's difficult.

Here we just avoid the loop with the x86 vector transform that conflicts with the general DAG
combine and preserve all of the existing behavior AFAICT otherwise.

Some tests that will probably fail if someone does try to restrict this in a more targeted way
for x86-only may be found in:

test/CodeGen/X86/combine-mul.ll
test/CodeGen/X86/vector-mul.ll
test/CodeGen/X86/widen_arith-5.ll

This should prevent the infinite looping seen with:
https://bugs.llvm.org/show_bug.cgi?id=35579

Differential Revision: https://reviews.llvm.org/D41040

llvm-svn: 320374
2017-12-11 15:19:31 +00:00
Alexander Potapenko c07e6a0eff [MSan] introduce getShadowOriginPtr(). NFC.
This patch introduces getShadowOriginPtr(), a method that obtains both the shadow and origin pointers for an address as a Value pair.
The existing callers of getShadowPtr() and getOriginPtr() are updated to use getShadowOriginPtr().

The rationale for this change is to simplify KMSAN instrumentation implementation.
In KMSAN origins tracking is always enabled, and there's no direct mapping between the app memory and the shadow/origin pages.
Both the shadow and the origin pointer for a given address are obtained by calling a single runtime hook from the instrumentation,
therefore it's easier to work with those pointers together.

Reviewed at https://reviews.llvm.org/D40835.

llvm-svn: 320373
2017-12-11 15:05:22 +00:00
Peter Smith 830a453554 [ELF] Improve comments in aarch64 errata fix test [NFC]
Comment improvements split out from review D36749. No changes to any non
comment line.

llvm-svn: 320372
2017-12-11 15:00:58 +00:00
Simon Pilgrim 5154d249a8 [X86] Add SAR/SHL/SHR schedule tests
llvm-svn: 320371
2017-12-11 14:56:44 +00:00
Simon Pilgrim 426add6915 [X86] Add RCL/RCR schedule tests
llvm-svn: 320370
2017-12-11 14:46:42 +00:00
Krzysztof Parzyszek 152414595b [Hexagon] Crash in instruction selection for insert_vector_elt for HVX
A wrong type was passed to insertVector, causing an out-of-bounds value
to be added an an operand to HexagonISD::INSERT. This later failed in
instruction selection.

llvm-svn: 320369
2017-12-11 14:46:06 +00:00
Nemanja Ivanovic 50d37a1129 [PowerPC] Sign-extend negative constant stores
Second part of https://reviews.llvm.org/D40348.
Revision r318436 has extended all constants feeding a store to 64 bits
to allow for CSE on the SDAG. However, negative constants were zero extended
which made the constant being loaded appear to be a positive value larger than
16 bits. This resulted in long sequences to materialize such constants
rather than simply a "load immediate". This patch just sign-extends those
updated constants so that they remain 16-bit signed immediates if they started
out that way.

llvm-svn: 320368
2017-12-11 14:35:48 +00:00
Pavel Labath c58a80ff47 Add a StringList constructor to Args class
Host::GetEnvironment returns a StringList, but the interface for
launching a process takes Args. The fact that we use two classes for
representing an environment is not ideal, but for now we should at least
have an easy way to convert between the two.

llvm-svn: 320366
2017-12-11 14:22:30 +00:00
Nemanja Ivanovic 25d9af0cb5 [DAGCombiner] Add combined indexed load to the work list
This commit is the first part of https://reviews.llvm.org/D40348.
In order to allow target combines to be performed on newly combined
indexed loads, add them back to the worklist. The remainder of the
above patch will be committed in subsequent revisions and will use
this. Test cases will be included with those follow-up commits.

llvm-svn: 320365
2017-12-11 14:16:02 +00:00
Roger Ferrer Ibanez 6f56d3eee8 [libcxx] Define istream_iterator equality comparison operators out-of-line
Currently libc++ defines operator== and operator!= as friend functions in the
definition of the istream_iterator class template. Such definition has a subtle
difference from an out-of-line definition required by the C++ Standard: these
functions can only be found by argument-dependent lookup, but not by qualified
lookup.

This patch changes the definition, so that it conforms to the C++ Standard and
adds a check involving qualified lookup to the test suite.

Patch contributed by Mikhail Maltsev.

Differential Revision: https://reviews.llvm.org/D40415

llvm-svn: 320363
2017-12-11 13:54:58 +00:00
Diana Picus 291e8d924f [ARM GlobalISel] Add test for a MOVTi16 pattern. NFC
Add test for matching an OR with 0xFFFF0000 to a MOVTi16.

llvm-svn: 320362
2017-12-11 13:28:45 +00:00
Simon Pilgrim 969850f514 [X86] Add fsgsbase schedule tests.
llvm-svn: 320361
2017-12-11 13:25:02 +00:00
Michael Kruse 5f0e8a46cf [ScopBuilder] Split statements on encountering store instructions.
Introduce -polly-stmt-granularity=store option.

Contributed-by: Nandini Singhal <cs15mtech01004@iith.ac.in>

Differential Revision: https://reviews.llvm.org/D37337

llvm-svn: 320360
2017-12-11 12:51:24 +00:00
Alex Bradbury dc31c61b18 [RISCV] Add custom CC_RISCV calling convention and improved call support
The TableGen-based calling convention definitions are inflexible, while
writing a function to implement the calling convention is very
straight-forward, and allows difficult cases to be handled more easily. With
this patch adds support for:
* Passing large scalars according to the RV32I calling convention
* Byval arguments
* Passing values on the stack when the argument registers are exhausted

The custom CC_RISCV calling convention is also used for returns.

This patch also documents the ABI lowering that a language frontend is 
expected to perform. I would like to work to simplify these requirements over 
time, but this will require further discussion within the LLVM community.

We add PendingArgFlags CCState, as a companion to PendingLocs.

The PendingLocs vector is used by a number of backends to handle arguments 
that are split during legalisation. However CCValAssign doesn't keep track of 
the original argument alignment. Therefore, add a PendingArgFlags vector which 
can be used to keep track of the ISD::ArgFlagsTy for every value added to 
PendingLocs.

Differential Revision: https://reviews.llvm.org/D39898

llvm-svn: 320359
2017-12-11 12:49:02 +00:00
Alex Bradbury bfb00d4c1c [RISCV] Allow lowering of dynamic_stackalloc, stacksave, stackrestore
llvm-svn: 320358
2017-12-11 12:38:17 +00:00
Alex Bradbury b014e3de52 [RISCV] Implement prolog and epilog insertion
As frame pointer elimination isn't implemented until a later patch and we make 
extensive use of update_llc_test_checks.py, this changes touches a lot of the 
RISC-V tests.

Differential Revision: https://reviews.llvm.org/D39849

llvm-svn: 320357
2017-12-11 12:34:11 +00:00
Simon Pilgrim 220b1c13bf [X86] Regenerate fsgsbase intrinsic tests. NFCI.
llvm-svn: 320356
2017-12-11 12:22:15 +00:00
Roger Ferrer Ibanez 5ea0f2501f [ARM] Use ADDCARRY / SUBCARRY
This is a preparatory step for D34515.

This change:
 - makes nodes ISD::ADDCARRY and ISD::SUBCARRY legal for i32
 - lowering is done by first converting the boolean value into the carry flag
   using (_, C) ← (ARMISD::ADDC R, -1) and converted back to an integer value
   using (R, _) ← (ARMISD::ADDE 0, 0, C). An ARMISD::ADDE between the two
   operations does the actual addition.
 - for subtraction, given that ISD::SUBCARRY second result is actually a
   borrow, we need to invert the value of the second operand and result before
   and after using ARMISD::SUBE. We need to invert the carry result of
   ARMISD::SUBE to preserve the semantics.
 - given that the generic combiner may lower ISD::ADDCARRY and
   ISD::SUBCARRYinto ISD::UADDO and ISD::USUBO we need to update their lowering
   as well otherwise i64 operations now would require branches. This implies
   updating the corresponding test for unsigned.
 - add new combiner to remove the redundant conversions from/to carry flags
   to/from boolean values (ARMISD::ADDC (ARMISD::ADDE 0, 0, C), -1) → C
 - fixes PR34045
 - fixes PR34564
 - fixes PR35103

Differential Revision: https://reviews.llvm.org/D35192

llvm-svn: 320355
2017-12-11 12:13:45 +00:00
Aleksandar Beserminji 92985796dc [mips] Minor update to the comment (NFC)
llvm-svn: 320354
2017-12-11 12:12:16 +00:00
Alex Bradbury 660bcceccf [RISCV] Support lowering FrameIndex
Introduces the AddrFI "addressing mode", which is necessary simply because 
it's not possible to write a pattern that directly matches a frameindex.

Ensure callee-saved registers are accessed relative to the stackpointer. This
is necessary as callee-saved register spills are performed before the frame
pointer is set.

Move HexagonDAGToDAGISel::isOrEquivalentToAdd to SelectionDAGISel, so we can 
make use of it in the RISC-V backend.

Differential Revision: https://reviews.llvm.org/D39848

llvm-svn: 320353
2017-12-11 11:53:54 +00:00
Diana Picus 775bb74379 [ARM GlobalISel] Add tests for PKHBT and PKHTB
Test (some of) the patterns for selecting PKHBT and PKHTB. The others
are just very similar to the ones we're testing and there would be
little value in covering them as well.

llvm-svn: 320352
2017-12-11 11:44:23 +00:00
Aleksandar Beserminji 8ee5296152 [mips] Removal of microMIPS64R6
microMIPS64R6 is removed from backend, and therefore frontend
will show an error when target is microMIPS64R6.

This is Clang part of patch.

Differential Revision: https://reviews.llvm.org/D35624

llvm-svn: 320351
2017-12-11 11:29:17 +00:00