087affe2f3
ARM: Add a better diagnostic for some out of range immediates.
...
As an example of how the custom DiagnosticType can be used to provide
better operand-mismatch diagnostics, add a custom diagnostic for
the imm0_15 operand class used for several system instructions.
Update the tests to expect the improved diagnostic.
rdar://8987109
llvm-svn: 159051
2012-06-22 23:56:48 +00:00
6c7279ec2e
Fix the encoding of the armv7m (MClass) for MSR registers other than aspr,
...
iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits.
llvm-svn: 158560
2012-06-15 22:14:44 +00:00
b0ec375b96
Replace assertion failure for badly formatted CPS instrution with error message.
...
llvm-svn: 158445
2012-06-14 10:48:04 +00:00
bde9176663
Fix typos found by http://github.com/lyda/misspell-check
...
llvm-svn: 157885
2012-06-02 10:20:22 +00:00
42b96d1b74
Mark a static array as const.
...
llvm-svn: 157368
2012-05-24 04:11:15 +00:00
f1b225d0e0
Fix the encoding of the armv7m (MClass) for MSR APSR writes which was missing
...
the 0b10 mask encoding bits. Make MSR APSR writes without a _<bits> qualifier
an alias for MSR APSR_nzcvq even though ARM as deprecated it use. Also add
support for suffixes (_nzcvq, _g, _nzcvqg) for APSR versions. Some FIXMEs in
the code for better error checking when versions shouldn't be used.
rdar://11457025
llvm-svn: 157019
2012-05-17 22:18:01 +00:00
5a719f9b9a
Fixed the LLVM ARM v7 assembler and instruction printer for 8-bit immediate offset addressing. The assembler and instruction printer were not properly handeling the #-0 immediate.
...
llvm-svn: 156608
2012-05-11 09:10:54 +00:00
c6f32b3295
ARM: Thumb add(sp plus register) asm constraints.
...
Make sure when parsing the Thumb1 sp+register ADD instruction that
the source and destination operands match. In thumb2, just use the
wide encoding if they don't. In Thumb1, issue a diagnostic.
rdar://11219154
llvm-svn: 155748
2012-04-27 23:51:36 +00:00
82f95ea2ad
Fix ARM assembly parsing for upper case condition codes on IT instructions.
...
llvm-svn: 155720
2012-04-27 17:34:01 +00:00
f435b09eaf
Refactor IT handling not to store the bottom bit of the condition code in the mask operand in the MCInst.
...
llvm-svn: 155700
2012-04-27 08:42:59 +00:00
ba5b0cc82e
Unify internal representation of ARM instructions with a register right-shifted by #32 . These are stored as shifts by #0 in the MCInst and correctly marshalled when transforming from or to assembly representation.
...
llvm-svn: 155565
2012-04-25 18:00:18 +00:00
3ec7c2aa84
Add ifdef around getSubtargetFeatureName in tablegen output file so that only targets that want the function get it. This prevents other targets from getting an unused function warning.
...
llvm-svn: 155538
2012-04-25 06:56:34 +00:00
5117ef7453
ARM: improved assembler diagnostics for missing CPU features.
...
When an instruction match is found, but the subtarget features it
requires are not available (missing floating point unit, or thumb vs arm
mode, for example), issue a diagnostic that identifies what the feature
mismatch is.
rdar://11257547
llvm-svn: 155499
2012-04-24 22:40:08 +00:00
003607f474
ARM handle :lower16: and :upper16: after a '#' prefix.
...
rdar://11252521
llvm-svn: 154862
2012-04-16 21:18:46 +00:00
673824b4a1
Wire up support for diagnostic ranges in the ARMAsmParser.
...
As an example, attach range info to the "invalid instruction" message:
$ clang -arch arm -c asm.c
asm.c:2:11: error: invalid instruction
__asm__("foo r0");
^
<inline asm>:1:2: note: instantiated into assembly here
foo r0
^~~
llvm-svn: 154765
2012-04-15 17:04:27 +00:00
ad66de155b
ARM add missing Thumb1 two-operand aliases for shift-by-immediate.
...
rdar://11222742
llvm-svn: 154457
2012-04-11 00:15:16 +00:00
aca6c822e6
Fix a number of problems with ARM fused multiply add/subtract instructions.
...
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676
llvm-svn: 154456
2012-04-11 00:13:00 +00:00
df5a244797
ARM fix cc_out operand handling for t2SUBrr instructions.
...
We were incorrectly conflating some add variants which don't have a
cc_out operand with the mirroring sub encodings, which do. Part of the
awesome non-orthogonality legacy of thumb1. Similarly, handling of
add/sub of an immediate was sometimes incorrectly removing the cc_out
operand for add/sub register variants.
rdar://11216577
llvm-svn: 154411
2012-04-10 17:31:55 +00:00
930f2f66e7
ARM assembly aliases for add negative immediates using sub.
...
'add r2, #-1024' should just use 'sub r2, #1024' rather than erroring out.
Thumb1 aliases for adding a negative immediate to the stack pointer,
also.
rdar://11192734
llvm-svn: 154123
2012-04-05 20:57:13 +00:00
3d00eecc53
ARM assembly parsing for 'msr' plain 'cpsr' operand.
...
Plain 'cpsr' is an alias for 'cpsr_fc'.
rdar://11153753
llvm-svn: 154080
2012-04-05 03:17:53 +00:00
fdaab531b7
ARM assembler should prefer non-aliases encoding of cmp.
...
When an immediate is both a value [t2_]so_imm and a [t2_]so_imm_neg,
we want to use the non-negated form to make sure we prefer the normal
encoding, not the aliased encoding via the negation of, e.g., 'cmp.w'.
llvm-svn: 153770
2012-03-30 19:59:02 +00:00
74005ae691
ARM can only use narrow encoding for low regs.
...
llvm-svn: 153765
2012-03-30 18:39:43 +00:00
def5e34812
ARM integrated assembler should encoding choice for add/sub imm.
...
For 'adds r2, r2, #56' outside of an IT block, the 16-bit encoding T2
can be used for this syntax. Prefer the narrow encoding when possible.
rdar://11156277
llvm-svn: 153759
2012-03-30 17:20:40 +00:00
199ab90946
ARM assembly parsing needs to be paranoid about negative immediates.
...
Make sure to treat immediates as unsigned when doing relative comparisons.
rdar://11153621
llvm-svn: 153753
2012-03-30 16:31:31 +00:00
0b0298302c
ARM assembly 'cmp lr, #0' should not encode using 'cmn'.
...
The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.
rdar://11129224
llvm-svn: 153689
2012-03-29 21:19:52 +00:00
1fcf5bcae1
Prune some includes
...
llvm-svn: 153502
2012-03-27 07:54:11 +00:00
816ca27ef6
Fix assembling ARM vst2 instructions with double-spaced registers.
...
llvm-svn: 153099
2012-03-20 17:41:51 +00:00
67e76babd3
ARM assembly, accept optional '#' on lane index number.
...
rdar://11057160
llvm-svn: 153053
2012-03-19 20:39:53 +00:00
905686a82a
ARM ldm/stm register lists can be out of order.
...
It's not a good style idea, as the registers will be laid down in memory in
numerical order, not the order they're in the list, but it's legal. vldm/vstm
are stricter.
rdar://11064740
llvm-svn: 152943
2012-03-16 20:48:38 +00:00
6d9766b355
Remove inadvertant commit.
...
llvm-svn: 152870
2012-03-15 23:00:30 +00:00
d28888dd77
ARM case-insensitive checking for APSR_nzcv.
...
rdar://11056591
llvm-svn: 152846
2012-03-15 21:34:14 +00:00
d74560b170
ARM aliases for pre-unified syntax fcmpz[sd] mnemonics.
...
rdar://11056647
llvm-svn: 152834
2012-03-15 20:48:18 +00:00
ed428bc1ce
ARM more NEON VLD/VST composite physical register refactoring.
...
Register pair, all lanes subscripting.
llvm-svn: 152157
2012-03-06 23:10:38 +00:00
13a292cc74
ARM refactor more NEON VLD/VST instructions to use composite physregs
...
Register pair VLD1/VLD2 all-lanes instructions. Kill off more of the
pseudos as a result.
llvm-svn: 152150
2012-03-06 22:01:44 +00:00
e5307f9019
ARM Refactor VLD/VST spaced pair instructions.
...
Use the new composite physical registers.
llvm-svn: 152063
2012-03-05 21:43:40 +00:00
c71bf4739a
ARM Remove a bit of dead code.
...
llvm-svn: 152061
2012-03-05 21:09:58 +00:00
c988e0c521
ARM refactor away a bunch of VLD/VST pseudo instructions.
...
With the new composite physical registers to represent arbitrary pairs
of DPR registers, we don't need the pseudo-registers anymore. Get rid of
a bunch of them that use DPR register pairs and just use the real
instructions directly instead.
llvm-svn: 152045
2012-03-05 19:33:30 +00:00
e55c556a24
Convert assert(0) to llvm_unreachable
...
llvm-svn: 149961
2012-02-07 02:50:20 +00:00
a2147ce313
Tidy up. One more return type mismatch fix.
...
llvm-svn: 149452
2012-01-31 23:51:09 +00:00
5e5eabb5ab
Keep source information, if available, around for ARM Fixups.
...
Adjust an example MachObjectWriter diagnostic to use the information
to issue a better message.
Before:
LLVM ERROR: unknown ARM fixup kind!
After:
x.s:6:5: error: unsupported relocation on symbol
beq bar
^
rdar://9800182
llvm-svn: 149093
2012-01-26 23:20:15 +00:00
c8f2b7877b
Tidy up. Fix mismatched return types for error handling.
...
llvm-svn: 149062
2012-01-26 15:56:45 +00:00
82f76d1275
ARM assemly parsing and validation of IT instruction.
...
"Although a Thumb2 instruction, the IT mnemonic shall be permitted in
ARM mode, and the condition verified to match the condition code(s)
on the following instruction(s)."
PR11853
llvm-svn: 148969
2012-01-25 19:52:01 +00:00
086cbfac7d
NEON VLD4(all lanes) assembly parsing and encoding.
...
llvm-svn: 148884
2012-01-25 00:01:08 +00:00
b78403ce48
NEON VLD3(all lanes) assembly parsing and encoding.
...
llvm-svn: 148882
2012-01-24 23:47:04 +00:00
8e2722cdb0
NEON VST4(one lane) assembly parsing and encoding.
...
llvm-svn: 148836
2012-01-24 18:53:13 +00:00
14952a0e32
NEON VLD4(one lane) assembly parsing and encoding.
...
llvm-svn: 148832
2012-01-24 18:37:25 +00:00
da70eac268
NEON VST4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148764
2012-01-24 00:58:13 +00:00
ed561fc850
NEON VLD4(multiple 4 element structures) assembly parsing.
...
llvm-svn: 148762
2012-01-24 00:43:17 +00:00
1e946a4f91
Tidy up. Remove some vertical space for readability.
...
llvm-svn: 148761
2012-01-24 00:43:12 +00:00
d3d36d9315
NEON VST3(single element from one lane) assembly parsing.
...
llvm-svn: 148755
2012-01-24 00:07:41 +00:00
1a74724fc9
NEON VST3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148748
2012-01-23 23:45:44 +00:00
ac2af3ffab
NEON VLD3(multiple 3-element structures) assembly parsing.
...
llvm-svn: 148745
2012-01-23 23:20:46 +00:00
a8b444b08b
NEON VLD3 lane-indexed assembly parsing and encoding.
...
llvm-svn: 148734
2012-01-23 21:53:26 +00:00
d28ef9ac46
Simplify some NEON assembly pseudo definitions.
...
Let the generic token alias definitions handle the data subtype
suffices. We don't need explicit versions for each.
llvm-svn: 148718
2012-01-23 19:39:08 +00:00
78dcaed8ca
Thumb2 'add rd, pc, imm' alternate form for 'adr' instruction.
...
llvm-svn: 148601
2012-01-21 00:07:56 +00:00
46a9f016c5
More dead code removal (using -Wunreachable-code)
...
llvm-svn: 148578
2012-01-20 21:51:11 +00:00
a9d36fbca7
NEON use vmov.i32 to splat some f32 values into vectors.
...
For bit patterns that aren't representable using the 8-bit floating point
representation for vmov.f32, but are representable via vmov.i32, treat
the .f32 syntax as an alias. Most importantly, this covers the case
'vmov.f32 Vd, #0.0'.
rdar://10616677
llvm-svn: 148556
2012-01-20 18:09:51 +00:00
235c8d2d94
ARM assembly diagnostic caret in better position for FPImm.
...
llvm-svn: 148459
2012-01-19 02:47:30 +00:00
94298a906a
Thumb2 alternate syntax for LDR(literal) and friends.
...
Explicit pc-relative syntax. For example, "ldrb r2, [pc, #-22]".
rdar://10250964
llvm-svn: 148432
2012-01-18 22:46:46 +00:00
486df738c3
Removing unused default switch cases in switches over enums that already account for all enumeration values explicitly.
...
(This time I believe I've checked all the -Wreturn-type warnings from GCC & added the couple of llvm_unreachables necessary to silence them. If I've missed any, I'll happily fix them as soon as I know about them)
llvm-svn: 148262
2012-01-16 23:24:27 +00:00
b982d8eb65
Fix malformed assert.
...
If anybody has strong feelings about 'default: assert(0 && "blah")' vs
'default: llvm_unreachable("blah")', feel free to regularize the instances of
each in this file.
llvm-svn: 147459
2012-01-03 19:03:59 +00:00
ea2319112f
ARM VFP assembly parsing and encoding for VCVT(float <--> fixed point).
...
rdar://10558523
llvm-svn: 147189
2011-12-22 22:19:05 +00:00
c4d8d2f155
Tidy up. Use predicate function a bit more liberally.
...
llvm-svn: 147184
2011-12-22 22:02:35 +00:00
489ed5929e
ARM pre-UAL aliases. fcmp[sd].
...
llvm-svn: 147158
2011-12-22 19:20:45 +00:00
12ccf45bbb
ARM assembler should accept shift-by-zero for any shifted-immediate operand.
...
Just treat it as-if the shift wasn't there at all. 'as' compatibility.
rdar://10604767
llvm-svn: 147153
2011-12-22 18:04:04 +00:00
21488b8839
ARM assembly parser canonicallize on 'lsl' for shift-by-zero form.
...
llvm-svn: 147152
2011-12-22 17:37:00 +00:00
3794d82af5
Tidy up. Trailing whitespace.
...
llvm-svn: 147151
2011-12-22 17:17:10 +00:00
62bffd8827
Nuke invalid comment from copy/paste.
...
llvm-svn: 147150
2011-12-22 17:04:50 +00:00
1152cc0cad
ARM asm parser should be more lenient w/ .thumb_func directive.
...
Rather than require the symbol to be explicitly an argument of the directive,
allow it to look ahead and grab the symbol from the next non-whitespace
line.
rdar://10611140
llvm-svn: 147100
2011-12-21 22:30:16 +00:00
8c59bbc1ed
Thumb2 assembly parsing of 'mov rd, rn, rrx'.
...
Maps to the RRX instruction. Missed this case earlier.
rdar://10615373
llvm-svn: 147096
2011-12-21 21:04:19 +00:00
b3ef713e44
Thumb2 assembly parsing of 'mov(register shifted register)' aliases.
...
These map to the ASR, LSR, LSL, ROR instruction definitions.
rdar://10615373
llvm-svn: 147094
2011-12-21 20:54:00 +00:00
7de7ab83fa
ARM assembly parsing allows constant expressions for lane indices.
...
llvm-svn: 147028
2011-12-21 01:19:23 +00:00
c5af54ec89
ARM NEON VLD2 assembly parsing for structure to all lanes, non-writeback.
...
llvm-svn: 147025
2011-12-21 00:38:54 +00:00
cd22e4a81e
ARM .req register name aliases are case insensitive, just like regnames.
...
llvm-svn: 147009
2011-12-20 23:11:00 +00:00
4eda145c7f
Move comment to appropriate place.
...
llvm-svn: 147000
2011-12-20 22:26:38 +00:00
2c59052984
ARM assembly parsing and encoding for VST2 single-element, double spaced.
...
llvm-svn: 146990
2011-12-20 20:46:29 +00:00
75e2ab5db2
ARM assembly parsing and encoding for VLD2 single-element, double spaced.
...
llvm-svn: 146983
2011-12-20 19:21:26 +00:00
135d244b56
First steps in ARM AsmParser support for .eabi_attribute and .arch
...
(Both used for Linux gnueabi)
No behavioral change yet (no tests need so far)
llvm-svn: 146977
2011-12-20 17:38:12 +00:00
e2ca9e5b5f
ARM assembly shifts by zero should be plain 'mov' instructions.
...
"mov r1, r2, lsl #0" should assemble as "mov r1, r2" even though it's
not strictly legal UAL syntax. It's a common extension and the friendly
thing to do.
rdar://10604663
llvm-svn: 146937
2011-12-20 00:59:38 +00:00
045b6c71a6
ARM NEON assembly aliases for VMOV<-->VMVN for i32 immediates.
...
e.g., "vmov.i32 d4, #-118" can be assembled as "vmvn.i32 d4, #117"
rdar://10603913
llvm-svn: 146925
2011-12-19 23:51:07 +00:00
8648c10184
ARM assembly parsing and encoding support for LDRD(label).
...
rdar://9932658
llvm-svn: 146921
2011-12-19 23:06:24 +00:00
e16acacc3a
ARM VFP pre-UAL mnemonic aliases for fmul[sd].
...
llvm-svn: 146892
2011-12-19 19:43:50 +00:00
92a939ae73
ARM VFP pre-UAL mnemonic aliases for fcpy[sd] and fdiv[sd].
...
llvm-svn: 146887
2011-12-19 19:02:41 +00:00
cef98cddbe
ARM NEON relax parse time diagnostics for alignment specifiers.
...
There's more variation that we need to handle. Error checking will need
to be on operand predicates.
llvm-svn: 146884
2011-12-19 18:31:43 +00:00
c2f16a3499
Silence warning.
...
llvm-svn: 146686
2011-12-15 21:54:55 +00:00
2f50e92f40
ARM NEON two-register double spaced register list parsing support.
...
llvm-svn: 146685
2011-12-15 21:44:33 +00:00
da51104282
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
...
llvm-svn: 146608
2011-12-14 23:35:06 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
...
llvm-svn: 146605
2011-12-14 23:25:46 +00:00
ab5830e51b
ARM assembler support for the target-specific .req directive.
...
rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
485e5622f4
Thumb2 assembler aliases for "mov(shifted register)"
...
rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
18bf363078
ARM LDM/STM system instruction variants.
...
rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
5ac89675a0
Thumb2 tweak for ccout handling in RSB parsing.
...
llvm-svn: 146516
2011-12-13 21:06:41 +00:00
1f1a3598c2
ARM thumb2 parsing of "rsb rd, rn, #0".
...
rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
2a2348e6c2
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146508
2011-12-13 20:13:48 +00:00
27a7489a03
LLVMBuild: Remove trailing newline, which irked me.
...
llvm-svn: 146409
2011-12-12 19:48:00 +00:00
54337b8617
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146300
2011-12-10 00:01:02 +00:00
8be2f6577e
ARM add some pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146296
2011-12-09 23:34:09 +00:00
ef70e9b704
ARM allows '' syntax, not just '#imm' for assembly.
...
Backwards compatibility with 'gas'. #imm is the preferered and documented
syntax, but lots of existing code uses the '$' prefix, so we should
support it if we can.
llvm-svn: 146285
2011-12-09 22:25:03 +00:00
8cc83fa1b7
ARM convenience aliases for VSQRT.
...
llvm-svn: 146201
2011-12-08 22:51:25 +00:00
ba7d6ed05d
ARM VSHR implied destination operand form aliases.
...
llvm-svn: 146192
2011-12-08 22:06:06 +00:00
Jim Grosbach