06bb798803
build/unittests: Fix llvm-config names for gtest libraries, and bring Makefile
...
library names in line with those used by CMake.
- Patch by Johannes Obermayr, with tweaks by me.
llvm-svn: 146706
2011-12-15 23:35:08 +00:00
c9e935c7e2
Move parts of lib/Target that use CodeGen into lib/CodeGen.
...
llvm-svn: 146702
2011-12-15 22:58:58 +00:00
c9bf1b1bff
Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.)
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llvm-svn: 146700
2011-12-15 22:56:53 +00:00
a47294e24d
ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.
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llvm-svn: 146699
2011-12-15 22:56:33 +00:00
7a9eb49a47
[asan] add the name of the module to the description of a global variable. This improves the readability of global-buffer-overflow reports.
...
llvm-svn: 146698
2011-12-15 22:55:55 +00:00
b3705e0b9e
Add MCTargetDesc library to Hexagon target
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llvm-svn: 146692
2011-12-15 22:29:08 +00:00
4a5c887370
ARM NEON VTBL/VTBX assembly parsing and encoding.
...
llvm-svn: 146691
2011-12-15 22:27:11 +00:00
cba8e8c3e0
Enable proper constant island alignment by default.
...
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.
llvm-svn: 146690
2011-12-15 22:14:45 +00:00
41dbf59e12
Add missing zmovl AVX patterns which were causing crashes.
...
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146689
2011-12-15 22:11:31 +00:00
cd1aba8b4d
[asan] fix a bug (issue 19) where dlclose and the following mmap caused a false positive. compiler part.
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llvm-svn: 146688
2011-12-15 21:59:03 +00:00
c2f16a3499
Silence warning.
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llvm-svn: 146686
2011-12-15 21:54:55 +00:00
2f50e92f40
ARM NEON two-register double spaced register list parsing support.
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llvm-svn: 146685
2011-12-15 21:44:33 +00:00
75ed9dcbc6
Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX.
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Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!
llvm-svn: 146684
2011-12-15 21:34:44 +00:00
6486165d57
Zap unnecessary semicolons.
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llvm-svn: 146682
2011-12-15 21:11:38 +00:00
918f976e66
Set specific target cpu for testcase.
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llvm-svn: 146678
2011-12-15 20:22:34 +00:00
2d6d3a2f96
Added test case for r146671.
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llvm-svn: 146675
2011-12-15 19:56:07 +00:00
f94cd19374
Use the proper comparator for set_intersection.
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llvm-svn: 146674
2011-12-15 19:26:23 +00:00
c44b5e469b
Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>.
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llvm-svn: 146671
2011-12-15 18:57:27 +00:00
7bbc1e56f5
Update DebugLoc while merging nodes at -O0.
...
Patch by Kyriakos Georgiou!
llvm-svn: 146670
2011-12-15 18:21:18 +00:00
750366f014
Add a test case to make sure that the nop really does follow the bl on ppc64 elf
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llvm-svn: 146666
2011-12-15 17:59:23 +00:00
cdd833eb28
Virtual table holder field is either metadata or null.
...
llvm-svn: 146665
2011-12-15 17:55:56 +00:00
9dd3f62b38
Ensure that the nop that should follow a bl call in PPC64 ELF actually does
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llvm-svn: 146664
2011-12-15 17:54:01 +00:00
c0f97e3dd4
Synthesize missing register class intersections.
...
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B. This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.
In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).
This introduces these synthetic register classes:
ARM:
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
GPRnopc_and_hGPR
GPRnopc_and_hGPR
hGPR_and_rGPR
tGPR_and_tcGPR
hGPR_and_tcGPR
X86:
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR64_NOSP_and_GR64_TC
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOSP_and_GR64_TC
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_NOSP
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR32_ABCD_and_GR32_NOAX
GR32_NOAX_and_GR32_TC
GR32_NOAX_and_GR32_NOSP
GR64_NOSP_and_GR64_TC
GR32_NOAX_and_GR32_NOREX
GR32_NOAX_and_GR32_NOREX_NOSP
GR64_NOREX_and_GR64_TC
GR64_NOREX_NOSP_and_GR64_TC
GR32_ABCD_and_GR32_NOAX
GR64_ABCD_and_GR64_TC
GR32_NOAX_and_GR32_TC
GR32_AD_and_GR32_NOAX
Other targets are unaffected.
llvm-svn: 146657
2011-12-15 16:48:55 +00:00
275e874c67
Pass optLevel to XCoreDAGToDAGISel.
...
Patch by Kyriakos Georgiou.
llvm-svn: 146656
2011-12-15 15:18:35 +00:00
ef7b2f2532
Fix test.
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llvm-svn: 146642
2011-12-15 04:52:47 +00:00
a45ab503f6
Make constant folding for GEPs a bit more aggressive.
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llvm-svn: 146639
2011-12-15 04:33:48 +00:00
2ec824966d
Don't try to form FGETSIGN after legalization; it is possible in some cases, but the existing code can't do it correctly. PR11570.
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llvm-svn: 146630
2011-12-15 02:07:20 +00:00
b7a0b89ff0
Use SmallVector/assign(), rather than std::vector/push_back().
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llvm-svn: 146627
2011-12-15 01:16:09 +00:00
1940baa76b
Add support for lowering fneg when AVX is enabled.
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rdar://10566486
llvm-svn: 146625
2011-12-15 01:02:25 +00:00
b33c297f14
Added InstCombine for "select cond, ~cond, x" type patterns
...
These can be reduced to "~cond & x" or "~cond | x"
llvm-svn: 146624
2011-12-15 00:56:45 +00:00
e7f329fa7a
Enable synthesis of FLOG2 and FEXP2 SelectionDAG nodes from libm calls. These are already marked as illegal by default.
...
llvm-svn: 146623
2011-12-15 00:54:12 +00:00
16ad2905a3
Make loop preheader insertion in LoopSimplify handle the case where the loop header is a landing pad correctly (by splitting the landingpad out of the loop header). Make some adjustments to the rest of LoopSimplify to make it clear that the rest of LoopSimplify isn't making bad assumptions about the presence of landing pads. PR11575.
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llvm-svn: 146621
2011-12-15 00:50:34 +00:00
db0f63e345
Re-re-enable compact unwind after fixing a failure in SingleSource/Benchmarks/Shootout-C++/except.cpp and friends. It was encoding the stored registers in the wrong order.
...
llvm-svn: 146617
2011-12-15 00:14:24 +00:00
dc785db0c3
Another improvement to the implementation of .incbin directive by avoiding a
...
buffer copy. Suggestion by Chris Lattner!
llvm-svn: 146614
2011-12-15 00:00:27 +00:00
ae94fb4009
The saved registers weren't being processed in the correct order. This lead to
...
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.
llvm-svn: 146612
2011-12-14 23:53:24 +00:00
75d7d5e988
Move Instruction::isSafeToSpeculativelyExecute out of VMCore and
...
into Analysis as a standalone function, since there's no need for
it to be in VMCore. Also, update it to use isKnownNonZero and
other goodies available in Analysis, making it more precise,
enabling more aggressive optimization.
llvm-svn: 146610
2011-12-14 23:49:11 +00:00
9efd7ebf0a
Consider CPE alignment in CreateNewWater().
...
An aligned constant pool entry may require extra alignment padding where
the new water is created. Take that into account when computing offset.
Also consider the alignment of other constant pool entries when
splitting a basic block. Alignment padding may make it necessary to
move the split point higher.
llvm-svn: 146609
2011-12-14 23:48:54 +00:00
da51104282
ARM NEON better assembly operand range checking for lane indices of VLD/VST.
...
llvm-svn: 146608
2011-12-14 23:35:06 +00:00
a8aa30b620
ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding.
...
llvm-svn: 146605
2011-12-14 23:25:46 +00:00
c268688643
Do not sink instruction, if it is not profitable.
...
On ARM, peephole optimization for ABS creates a trivial cfg triangle which tempts machine sink to sink instructions in code which is really straight line code. Sometimes this sinking may alter register allocator input such that use and def of a reg is divided by a branch in between, which may result in extra spills. Now mahine sink avoids sinking if final sink destination is post dominator.
Radar 10266272.
llvm-svn: 146604
2011-12-14 23:20:38 +00:00
d647109ff9
Add a blurb about MachineInstr bundling support.
...
llvm-svn: 146603
2011-12-14 22:57:45 +00:00
b108aaebbe
Reapply r146481 with a fix to create the Builder value in the correct place and
...
with the correct iterator.
<rdar://problem/10530851>
llvm-svn: 146600
2011-12-14 22:45:33 +00:00
ad41ab5015
Improve the implementation of .incbin directive by replacing a loop by using
...
getStreamer().EmitBytes. Suggestion by Benjamin Kramer!
llvm-svn: 146599
2011-12-14 22:34:45 +00:00
e0ced62119
LSR: Fold redundant bitcasts on-the-fly.
...
llvm-svn: 146597
2011-12-14 22:07:19 +00:00
bb18fb4f52
ARM NEON fix alignment encoding for VST2 w/ writeback.
...
Add tests for w/ writeback instruction parsing and encoding.
llvm-svn: 146594
2011-12-14 21:49:24 +00:00
109f25c966
Add the .incbin directive which takes the binary data from a file and emits
...
it to the streamer. rdar://10383898
llvm-svn: 146592
2011-12-14 21:47:48 +00:00
8e987f5e25
Nuke old code. Missed in last commit.
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llvm-svn: 146590
2011-12-14 21:41:32 +00:00
c984bf8fb0
Add high level description of MachineInstr bundles.
...
llvm-svn: 146589
2011-12-14 21:32:14 +00:00
88ac761aa4
ARM NEON refactor VST2 w/ writeback instructions.
...
In addition to improving the representation, this adds support for assembly
parsing of these instructions.
llvm-svn: 146588
2011-12-14 21:32:11 +00:00
b7ec06c5c9
ARM NEON improve factoring a bit. No functional change.
...
llvm-svn: 146585
2011-12-14 20:59:15 +00:00
da103bf9ec
Model ARM predicated write as read-mod-write. e.g.
...
r0 = mov #0
r0 = moveq #1
Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.
llvm-svn: 146583
2011-12-14 20:00:08 +00:00
8d24618975
ARM NEON VST2 assembly parsing and encoding.
...
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.
llvm-svn: 146579
2011-12-14 19:35:22 +00:00
d7b2bb3bdd
Fix for bug #11429 : Wrong behaviour for switches. Small improvement for code size heuristics.
...
llvm-svn: 146578
2011-12-14 19:19:17 +00:00
bd944b4153
It turns out that clang does use pointer-to-function types to
...
point to ARC-managed pointers sometimes. This fixes rdar://10551239.
llvm-svn: 146577
2011-12-14 19:10:53 +00:00
e5585e8fed
Fix speling and 80-col.
...
llvm-svn: 146575
2011-12-14 18:49:13 +00:00
bff84e1914
Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object
...
emission is not supported yet, but a patch that adds the support should follow
soon.
llvm-svn: 146572
2011-12-14 18:26:41 +00:00
4288b9786f
Fix copy/pasto that skipped the 'modify' step.
...
llvm-svn: 146571
2011-12-14 18:12:37 +00:00
1bb6e066f6
ARM/Thumb2 mov vs. mvn alias goes both ways.
...
llvm-svn: 146570
2011-12-14 17:56:51 +00:00
ded6160473
VFP2 is required for FP loads. Noticed by inspection.
...
llvm-svn: 146569
2011-12-14 17:55:03 +00:00
fce28914ea
Tidy up.
...
llvm-svn: 146568
2011-12-14 17:32:02 +00:00
a342667fd0
ARM/Thumb2 'cmp rn, #imm' alias to cmn.
...
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.
rdar://10552389
llvm-svn: 146567
2011-12-14 17:30:24 +00:00
a26979be29
Fix 80-column violation and extraneous brackets.
...
llvm-svn: 146566
2011-12-14 17:26:05 +00:00
9aaec15ce3
Vectors are not aggregate types (see isAggregateType).
...
llvm-svn: 146561
2011-12-14 15:44:20 +00:00
4c5ab7bb38
llvm/lib/CodeGen: Fix cmake build since r146542.
...
llvm-svn: 146550
2011-12-14 03:50:53 +00:00
fdeaf25827
Fix a stupid typo in MemDepPrinter.
...
llvm-svn: 146549
2011-12-14 02:54:39 +00:00
6512cd4366
Add missing cases to SDNode::getOperationName(). Patch by Micah Villmow.
...
llvm-svn: 146548
2011-12-14 02:28:54 +00:00
87975df580
Allow target to specify register output dependency. Still default to one.
...
llvm-svn: 146547
2011-12-14 02:28:53 +00:00
2be88f1301
Revert r146481 to review possible miscompilations.
...
llvm-svn: 146546
2011-12-14 02:18:26 +00:00
27a9762b3c
Disable to review some failures.
...
llvm-svn: 146545
2011-12-14 02:16:54 +00:00
ab5830e51b
ARM assembler support for the target-specific .req directive.
...
rdar://10549683
llvm-svn: 146543
2011-12-14 02:16:11 +00:00
7fae11b231
- Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
...
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.
llvm-svn: 146542
2011-12-14 02:11:42 +00:00
4020ae75ea
Add newline at EOF.
...
llvm-svn: 146538
2011-12-14 01:34:39 +00:00
cfde1a26b4
DW_AT_virtuality is also defined to be constant, not flag.
...
llvm-svn: 146534
2011-12-14 00:56:07 +00:00
8f92ce6e39
Per discussion on the list, remove BitcodeVerify pass to reimplement as a free function.
...
llvm-svn: 146531
2011-12-14 00:29:31 +00:00
ac6ae7302d
[asan] remove .preinit_array from the compiler module (it breaks .so builds). This should be done in the run-time.
...
llvm-svn: 146527
2011-12-14 00:01:51 +00:00
bc96f37253
llvm-nm: refactor in order to support reading files from stdin.
...
llvm-svn: 146524
2011-12-13 23:17:29 +00:00
4f8a832c19
Support/FileSystem: Add file_magic and move a vew clients over to it.
...
llvm-svn: 146523
2011-12-13 23:17:12 +00:00
a2755f8efa
Support/Program: Make Change<stream>ToBinary return error_code.
...
llvm-svn: 146522
2011-12-13 23:16:49 +00:00
7dfbeda68e
Cleanup whitespace.
...
llvm-svn: 146521
2011-12-13 23:16:15 +00:00
485e5622f4
Thumb2 assembler aliases for "mov(shifted register)"
...
rdar://10549767
llvm-svn: 146520
2011-12-13 22:45:11 +00:00
18bf363078
ARM LDM/STM system instruction variants.
...
rdar://10550269
llvm-svn: 146519
2011-12-13 21:48:29 +00:00
6eb142a616
Thumb2 pre/post indexed stores can be from any non-PC GPR.
...
rdar://10549786
llvm-svn: 146518
2011-12-13 21:10:25 +00:00
dce106940e
Test for 146516
...
llvm-svn: 146517
2011-12-13 21:06:59 +00:00
5ac89675a0
Thumb2 tweak for ccout handling in RSB parsing.
...
llvm-svn: 146516
2011-12-13 21:06:41 +00:00
1f1a3598c2
ARM thumb2 parsing of "rsb rd, rn, #0".
...
rdar://10549741
llvm-svn: 146515
2011-12-13 20:50:38 +00:00
4b0844e191
ARM NEON two-operand aliases for VQDMULH.
...
llvm-svn: 146514
2011-12-13 20:40:37 +00:00
561e4e18cf
ARM pre-UAL NEG mnemonic for convenience when porting old code.
...
llvm-svn: 146511
2011-12-13 20:23:22 +00:00
2a2348e6c2
ARM add some more pre-UAL VFP mnemonics for convenience when porting old code.
...
llvm-svn: 146508
2011-12-13 20:13:48 +00:00
9227f39c53
ARM add more 'gas' compatibility aliases for NEON instructions.
...
llvm-svn: 146507
2011-12-13 20:08:32 +00:00
30c85d1945
mention AddressSanitizer in 3.1 release notes
...
llvm-svn: 146505
2011-12-13 19:46:24 +00:00
21dc2be97a
[asan] report an error if blacklist file contains a malformed regex. fixes asan issue 17
...
llvm-svn: 146503
2011-12-13 19:34:53 +00:00
563de603f7
[fast-isel] Unaligned loads of floats are not supported. Therefore, convert to a regular
...
load and then move the result from a GPR to a FPR.
llvm-svn: 146502
2011-12-13 19:22:14 +00:00
9f2a83eb59
Rip llvm 3.0 out of the release notes, making room for LLVM 3.1
...
llvm-svn: 146493
2011-12-13 17:55:30 +00:00
b941674aa4
[fast-isel] Remove SelectInsertValue() as fast-isel wasn't designed to handle
...
instructions that define aggregate types.
llvm-svn: 146492
2011-12-13 17:45:06 +00:00
2f1d93ffe0
Avoid using the 'insertvalue' instruction here.
...
Fast ISel isn't able to handle 'insertvalue' and it causes a large slowdown
during -O0 compilation. We don't necessarily need to generate an aggregate of
the values here if they're just going to be extracted directly afterwards.
<rdar://problem/10530851>
llvm-svn: 146481
2011-12-13 09:22:43 +00:00
cb91849fc7
DW_AT_accessibility is "constant" class, not form class, so it may not use
...
DW_FORM_flag. Use DW_FORM_data1 for one byte.
llvm-svn: 146475
2011-12-13 05:09:11 +00:00
7200123fa3
Add test/MC/Mips/dg.exp.
...
llvm-svn: 146472
2011-12-13 04:12:49 +00:00
341850fdc6
Move direct object emitter test to directory test/MC/Mips. Rename it to
...
elf-relsym.ll.
llvm-svn: 146470
2011-12-13 03:50:34 +00:00
5e9d16cb53
Expand .cprestore directive to multiple instructions if the offset does not fit
...
in a 16-bit field.
llvm-svn: 146469
2011-12-13 03:09:05 +00:00
e41963ce47
Relocation against a symbol, instead of against section. We had some extreme
...
test cases where there were a lot of relocations applied relative to a large
rodata section. Gas would create a symbol for each of these whereas we would
be relative to the beginning of the rodata section. This change mimics what
gas does.
Patch by Jack Carter.
llvm-svn: 146468
2011-12-13 02:27:40 +00:00
Daniel Dunbar