llvm-project

Commit Graph

Author	SHA1	Message	Date
Oliver Stannard	d4e0a4fd2c	[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5 Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions when targeting ARMv8, but they are actually present on any target with FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an M-profile core, but they have the same instructions so we model them both as FPARMv8 in the ARM backend. llvm-svn: 218763	2014-10-01 13:13:18 +00:00
Chad Rosier	b1bbf6f8ce	[AArch32] Add support for FP rounding operations for ARMv8/AArch32. Phabricator Revision: http://reviews.llvm.org/D4935 llvm-svn: 215772	2014-08-15 21:38:16 +00:00

Author

SHA1

Message

Date

Oliver Stannard

d4e0a4fd2c

[ARM] Allow selecting VRINT[APMXZR] and VCVT[BT] instructions for FPv5

Currently, we only codegen the VRINT[APMXZR] and VCVT[BT] instructions
when targeting ARMv8, but they are actually present on any target with
FP-ARMv8. Note that FP-ARMv8 is called FPv5 when is is part of an
M-profile core, but they have the same instructions so we model them
both as FPARMv8 in the ARM backend.

llvm-svn: 218763

2014-10-01 13:13:18 +00:00

Chad Rosier

b1bbf6f8ce

[AArch32] Add support for FP rounding operations for ARMv8/AArch32.

Phabricator Revision: http://reviews.llvm.org/D4935

llvm-svn: 215772

2014-08-15 21:38:16 +00:00

2 Commits