Commit Graph

423179 Commits

Author SHA1 Message Date
Nikita Popov 9678936f18 [DAGCombine] Fold (X & ~Y) | Y with truncated not
This extends the (X & ~Y) | Y to X | Y fold to also work if ~Y is
a truncated not (when taking into account the mask X). This is
done by exporting the infrastructure added in D124856 and reusing
it here.

I've retained the old value of AllowUndefs=false, though probably
this can be switched to true with extra test coverage.

Differential Revision: https://reviews.llvm.org/D124930
2022-05-05 11:10:11 +02:00
Florian Hahn 6bd2b70877
[SimpleLoopUnswitch] Add freeze if branch execs for partial unswitching.
We cannot skip the freezing the condition if the unswitched branch
executes, if the condition is a chain of ANDs/ORs. For example, if if we
have an AND %c1, %c2 with  %c1 == undef and %c2 == 0, there would be no
branch on undef in the original code, but a branch on undef if we
unswitch %c1.

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D124603
2022-05-05 09:44:07 +01:00
Jean Perier b910cf986a [flang] use 1-based dim in transformational runtime error msg
Flang transformational runtime was previously reporting conformity
issues in a zero based fashion to describe which dimension is non
conformant. This may confuse Fortran user, especially when the message
is about a dimension other than the first one.

Differential Revision: https://reviews.llvm.org/D124941
2022-05-05 10:33:14 +02:00
Adrian Kuegel cc344d262a [clang] Add static_cast to fix Bazel build.
Differential Revision: https://reviews.llvm.org/D124995
2022-05-05 10:29:47 +02:00
Matthias Springer e300682597 [mlir][scf][bufferize] Update verifyAnalysis error message
The previous error message was technically incorrect. We do not compare equivalence of YieldOp operands and ForOp operands.

Differential Revision: https://reviews.llvm.org/D124934
2022-05-05 16:56:50 +09:00
Matthias Springer 417e1c7d52 [mlir][scf][bufferize][NFC] Split ForOp bufferization into smaller functions
This is in preparation of WhileOp bufferization, which reuses these functions.

Differential Revision: https://reviews.llvm.org/D124933
2022-05-05 16:55:44 +09:00
Matthias Springer f178c386f5 [mlir][scf][bufferize][NFC] Simplify verifyAnalysis implementation
Differential Revision: https://reviews.llvm.org/D124928
2022-05-05 16:51:10 +09:00
Nikita Popov 47c559d6c1 [SCEV] Fold umin_seq to umin using implied poison reasoning
Similar to how we convert logical and/or to bitwise and/or, we should
also convert umin_seq to umin based on implied poison reasoning. In
%x umin_seq %y, if %y being poison implies %x being poison, then we
don't need the sequential evaluation: Having %y contribute towards
the result will never make the result more poisonous. An important
corollary of this is that if %y is never poison, we also don't need
the sequential evaluation.

This avoids some of the regressions in D124910.

Differential Revision: https://reviews.llvm.org/D124921
2022-05-05 09:43:49 +02:00
serge-sans-paille f416e57339 [lldb] Fix ppc64 detection in lldb
Currently, ppc64le and ppc64 (defaulting to big endian) have the same
descriptor, thus the linear scan always return ppc64le. Handle that through
subtype.

This is a recommit of f114f00948 with a new test
setup that doesn't involves (unsupported) corefiles.

Differential Revision: https://reviews.llvm.org/D124760
2022-05-05 09:22:02 +02:00
Chuanqi Xu 405bf90235 [NFC] [Pipelines] Hoist CoroCleanup as Module Pass
This is similar to previous patch https://reviews.llvm.org/D123925. It
could also reduce the time we call declaresCoroCleanupIntrinsics. And it
is helpful for further changes.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D124362
2022-05-05 15:15:09 +08:00
Chuanqi Xu 7d40f562e7 [Pipelines] Hoist CoroCleanup to avoid blocking optimizations
CoroCleanup is designed to lowering all the remaining coroutine
intrinsics. It is required to run after CoroSplit only. However, the
position of CoroCleanup now is far too late. The downside here is that
the unlowered coroutine instrincs might blocking other optimizations
too. So it should be a pure win to hoist the position of CoroCleanup.

Reviewed By: aeubanks

Differential Revision: https://reviews.llvm.org/D124360
2022-05-05 15:13:27 +08:00
Zakk Chen 6c10014f1d [RISCV][Clang] add more tests for clang driver. (NFC)
Test experimental arch, Zfh, Zfmin and Zve arch.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D124611
2022-05-04 23:55:52 -07:00
Serge Pavlov 83914ee96f [InstCombine] Remove side effect of replaced constrained intrinsics
If a constrained intrinsic call was replaced by some value, it was not
removed in some cases. The dangling instruction resulted in useless
instructions executed in runtime. It happened because constrained
intrinsics usually have side effect, it is used to model the interaction
with floating-point environment. In some cases it is correct behavior
but often the side effect is actually absent or can be ignored.

This change adds specific treatment of constrained intrinsics so that
their side effect can be removed if it actually absents.

Differential Revision: https://reviews.llvm.org/D118426
2022-05-05 12:02:42 +07:00
Mariusz Sikora 2417de2758 [AMDGPU] Use d16 flag for image.sample instructions
Image.sample instruction can be forced to return half type instead of
float when d16 flag is enabled.

This patch adds new pattern in InstCombine to detect if output of
image.sample is used later only by fptrunc which converts the type
from float to half. If pattern is detected then fptrunc and image.sample
are combined to single image.sample which is returning half type.
Later in Lowering part d16 flag is added to image sample intrinsic.

Differential Revision: https://reviews.llvm.org/D124232
2022-05-05 06:29:19 +02:00
Wael Yehia 2407c13aa4 [AIX][PGO] Enable linux style PGO on AIX
This patch switches the PGO implementation on AIX from using the runtime
registration-based section tracking to the __start_SECNAME/__stop_SECNAME
based. In order to enable the recognition of __start_SECNAME/__stop_SECNAME
symbols in the AIX linker, the -bdbg:namedsects:ss needs to be used.

Reviewed By: jsji, MaskRay, davidxl

Differential Revision: https://reviews.llvm.org/D124857
2022-05-05 04:10:39 +00:00
Eric Li 58abe36ae7 [clang][dataflow] Add flowConditionIsTautology function
Provide a way for users to check if a flow condition is
unconditionally true.

Differential Revision: https://reviews.llvm.org/D124943
2022-05-05 03:57:43 +00:00
Patryk Wychowaniec 6641c57aeb [AVR] Always expand STDSPQRr & STDWSPQRr
Currently, STDSPQRr and STDWSPQRr are expanded only during
AVRFrameLowering - this means that if any of those instructions happen
to appear _outside_ of the typical FrameSetup / FrameDestroy
context, they wouldn't get substituted, eventually leading to a crash:

```
LLVM ERROR: Not supported instr: <MCInst XXX <MCOperand Reg:1>
<MCOperand Imm:15> <MCOperand Reg:53>>
```

This commit fixes this issue by moving expansion of those two opcodes
into AVRExpandPseudo.

This bug was originally discovered due to the Rust compiler_builtins
library. Its 0.1.37 release contained a 128-bit software
division/remainder routine that exercised this buggy branch in the code.

Reviewed By: benshi001

Differential Revision: https://reviews.llvm.org/D123528
2022-05-05 03:10:59 +00:00
Lian Wang 8bb10436ab [RISCV][NFC] Use true_mask replace riscv_vmset_vl in defined patterns.
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D124660
2022-05-05 03:05:52 +00:00
Phoebe Wang aa25b55bde [X86] Add `void` to void function. NFC 2022-05-05 10:58:46 +08:00
Luo, Yuanke 373ce14760 [X86][AMX] Replace PXOR instruction with SET0 in AMX pre config.
To generate zero value, the PXOR instruction need 3 operands that is
tied to the same vreg. If is not good in SSA form and with undef value
two address instruction pass may convert
`%0:vr128 = PXORrr undef %0, undef %0`
to `%1:vr128 = PXORrr undef %1:vr128(tied-def 0), undef %0:vr128`.
It is not expected.
It can be simplified to SET0 instruction which only take 1 destination
operand. It should be more friendly to two address instruction pass and
register allocation pass.
`%0:vr128 = V_SET0`
Also add AVX1 code path so that it is consistant to other code.

Differential Revision: https://reviews.llvm.org/D124903
2022-05-05 10:44:57 +08:00
Ben Shi dc66897d4c [Disassembler][AVR] Remove unused static functions
The unused static functions cause failures on some build machines.
2022-05-05 02:20:27 +00:00
Craig Topper 589517925b [X86] Call initializeX86PreTileConfigPass from LLVMInitializeX86Target.
Without this, the pass doesn't show up in print-before/after-all.

Differential Revision: https://reviews.llvm.org/D124973
2022-05-04 19:09:06 -07:00
Craig Topper 572dfef1db [SelectionDAG] Use llvm::any_of to simplify a loop. NFC 2022-05-04 19:09:06 -07:00
Ben Shi b1dcd6bafb [MC][AVR] Implement decoding ST/LD
Reviewed By: aykevl, dylanmckay

Differential Revision: https://reviews.llvm.org/D123476
2022-05-05 01:53:59 +00:00
Ben Shi cef2739d68 [MC][AVR] Implement decoding STD/LDD
Reviewed By: aykevl, dylanmckay

Differential Revision: https://reviews.llvm.org/D123442
2022-05-05 01:53:49 +00:00
Alexander Shaposhnikov ec7122f64b [InstCombine] Fold ((A&B)^C)|B
Fold ((A&B)^C)|B into C|B.

https://alive2.llvm.org/ce/z/zSGSor

This addresses the issue https://github.com/llvm/llvm-project/issues/55169

Test plan: ninja check-all

Differential revision: https://reviews.llvm.org/D124710
2022-05-05 00:56:20 +00:00
Ayke van Laethem 514371c370
[compiler-rt][AVR] Fix avr_SOURCES CMake variable
D123200 did not include the generic sources, which means that only the
AVR-specific sources were compiled. With this change, generic sources
are included as expected.

Tested with the following commands:

    cmake -G Ninja -DCOMPILER_RT_DEFAULT_TARGET_TRIPLE=avr -DCOMPILER_RT_BAREMETAL_BUILD=1 -DCMAKE_C_COMPILER=clang-14 -DCMAKE_C_FLAGS="--target=avr -mmcu=avr5 -nostdlibinc -mdouble=64" ../path/to/builtins

    ninja

Differential Revision: https://reviews.llvm.org/D124969
2022-05-05 02:29:04 +02:00
Craig Topper 60cb489685 [RISCV] Use movImm went multiplying by simm12 in getVLENFactoredAmount.
No reason to special case simm12, movImm handles all immediates.

This also fixe a bug that we weren't passing the frame-setup/destroy
flag to movImm when we were calling it.
2022-05-04 17:23:22 -07:00
Alexander Shaposhnikov 640f1e0829 [InstCombine][NFC] Update comment in and-xor-or.ll 2022-05-05 00:07:49 +00:00
Alexander Shaposhnikov 46bef4d713 [InstCombine][NFC] Add baseline tests for folds of ((A&B)^C)|B
Differential revision: https://reviews.llvm.org/D124709

Test plan: make check-all
2022-05-05 00:04:33 +00:00
Nico Weber 895a72111b [lld/mac] Support writing zippered dylibs and bundles
With -platform_version flags for two distinct platforms,
this writes a LC_BUILD_VERSION header for each.

The motivation is that this is needed for self-hosting with lld as linker
after D124059.

To create a zippered output at the clang driver level, pass

    -target arm64-apple-macos -darwin-target-variant arm64-apple-ios-macabi

to create a zippered dylib.

(In Xcode's clang, `-darwin-target-variant` is spelled just `-target-variant`.)

(If you pass `-target arm64-apple-ios-macabi -target-variant arm64-apple-macos`
instead, ld64 crashes!)

This results in two -platform_version flags being passed to the linker.

ld64 also verifies that the iOS SDK version is at least 13.1. We don't do that
yet. But ld64 also does that for other platforms and we don't. So we need to
do that at some point, but not in this patch.

Only dylib and bundle outputs can be zippered.

I verified that a Catalyst app linked against a dylib created with

    clang -shared foo.cc -o libfoo.dylib \
          -target arm64-apple-macos \
          -target-variant arm64-apple-ios-macabi \
          -Wl,-install_name,@rpath/libfoo.dylib \
          -fuse-ld=$PWD/out/gn/bin/ld64.lld

runs successfully. (The app calls a function `f()` in libfoo.dylib
that returns a const char* "foo", and NSLog(@"%s")s it.)

ld64 is a bit more permissive when writing zippered outputs,
see references to "unzippered twins". That's not implemented yet.
(If anybody wants to implement that, D124275 is a good start.)

Differential Revision: https://reviews.llvm.org/D124887
2022-05-04 19:23:35 -04:00
Nico Weber ddef1ed4e7 [llvm-otool] Make `llvm-otool -l` output compatible with otool for LC_BUILD_VERSION
Namely, only "symbolize" platform and tool names if `-v` is passed.

(`llvm-otool -lv` output still isn't quite the same as `otool -lv` output, but
`-v` output is arguably for consumption by humans, so I'm not changing that
at this point. Someone else could change it if it was important to them.)

Differential Revision: https://reviews.llvm.org/D124920
2022-05-04 19:19:09 -04:00
Craig Topper ef849f5048 [PowerPC] Re-run update_mir_test_checks.py on nofpexcept.ll. NFC
This test was previously generated by the script, but the script
now uses CHECK-NEXT instead of CHECK.

This is preparation for a strictfp related patch I'm working on.
2022-05-04 16:17:14 -07:00
H.J. Lu f52e365092 [sanitizer] Use newfstatat for x32
Since newfstatat is supported on x32, use it for x32.

Differential Revision: https://reviews.llvm.org/D124968
2022-05-04 15:54:42 -07:00
Jason Molenda a6553d97df Remove expected fail for TestStepNoDebug on AArch64
My fix in https://reviews.llvm.org/D124492 should fix
this - I got an "unexpected pass" failure from an
Aarch64 Ubuntu bot when I landed my fix.
2022-05-04 15:28:02 -07:00
Junfeng Dong a0fb387941 [DebugInfo] Give warning instead of error for premature terminator in .debug_aranges section.
llvm-profgen gives error message when the input binary contains premature terminator in .debug_aranges section. These zero length items point to some rodata with zero size type in embed Rust Library. Considering Zero-Sized Types are a valid feature in Rust. They are not real error. This change makes the "error:" message into a warning to avoid misleading.

Why do we still want a warning on such case? because it doesn't follow dwarf standard.  https://bugs.llvm.org/show_bug.cgi?id=46805 contains early discussion.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D124121
2022-05-04 15:21:58 -07:00
Jez Ng 19bb38b9c9 [lld-macho][nfc] Set test min version to 11.0
The arm64-apple-macos triple is only valid for versions >= 11.0. (If
one passes arm64-apple-macos10.15 to llvm-mc, the output's min version is still
11.0). In order to write tests easily for both target archs, let's up the
default min version in our tests.

Reviewed By: #lld-macho, thakis

Differential Revision: https://reviews.llvm.org/D124562
2022-05-04 18:01:34 -04:00
Jason Molenda df552edb08 Update the CFA to use $sp when $fp is restored on arm64
In UnwindAssemblyInstEmulation we correctly recognize when a LDP
restores the fp & lr in an epilogue, and mark them as having the
caller's contents now, but we don't update the CFA register rule
at that point to indicate that the CFA is now calculated in terms
of $sp.  This doesn't impact the backtrace because the register
contents are all <same> now, but it can confuse the stepper when
the StackID changes mid-epilogue.

Differential Revision: https://reviews.llvm.org/D124492
rdar://92064415
2022-05-04 14:54:17 -07:00
Zixu Wang cb5bb28511 Revert "Revert "[clang][extract-api] Use relative includes""
Reapply the change after fixing sanitizer errors.
The original problem was that `StringRef`s in `Matches` are pointing to
temporary local `std::string`s created by `path::convert_to_slash` in
the regex match call. This patch does the conversion up front in
container `FilePath`.

This reverts commit 2966f0fa50.

Differential Revision: https://reviews.llvm.org/D124964
2022-05-04 14:52:45 -07:00
Philip Reames 18ed2ee80c [RISCV] Add a version of insertVSETVLI which uses an iterator [NFC]
This is to simplify the final version of D124869.
2022-05-04 14:48:31 -07:00
Stanislav Mekhanoshin 63f21f4cc7 [AMDGPU] Handle LDS DMA and LDS_DIRECT hazards
There shall be 1 wait state between M0 write and LDS DMA/LDS_DIRECT use.

Differential Revision: https://reviews.llvm.org/D124550
2022-05-04 14:45:16 -07:00
Jon Chesterfield bc78c09952 [amdgpu] Elide module lds allocation in kernels with no callees
Introduces a string attribute, amdgpu-requires-module-lds, to allow
eliding the module.lds block from kernels. Will allocate the block as before
if the attribute is missing or has its default value of true.

Patch uses the new attribute to detect the simplest possible instance of this,
where a kernel makes no calls and thus cannot call any functions that use LDS.

Tests updated to match, coverage was already good. Interesting cases is in
lower-module-lds-offsets where annotating the kernel allows the backend to pick
a different (in this case better) variable ordering than previously. A later
patch will avoid moving kernel variables into module.lds when the kernel can
have this attribute, allowing optimal ordering and locally unused variable
elimination.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D122091
2022-05-04 22:42:07 +01:00
Craig Topper 411bb42eed [RISCV] Add a special case to treat riscv-v-vector-bits-min=-1 as meaning use Zvl*b value.
riscv-v-vector-bits-min is primarily used to opt-in to the
autovectorizer. The vector width can be determined from Zvl*b.

This patch adds support treating -1 as meaning use Zvl*b so we can
still opt-in to autovectorization without needing to repeat a
vector width already given by Zvl*b or -mcpu.

Reviewed By: reames

Differential Revision: https://reviews.llvm.org/D124960
2022-05-04 14:26:45 -07:00
Congzhe Cao 5e004fb787 [LoopCacheAnalysis][NFC] Add a test case for improved loop cache analysis cost calculation
Added a motivating test case for D123400 where the loopnest has a
suboptimal loop order j-i-k. After D123400 we ensure that the order
of loop cache analysis output is loop i-j-k, despite the suboptimal
order in the original loopnest.

Reviewed By: bmahjour, #loopoptwg

Differential Revision: https://reviews.llvm.org/D122776
2022-05-04 17:13:10 -04:00
David Green f848798b7d [ARM] Delay creation of MVE Imm shifts to legalization
The reasoning for creating VSHLIMM/VSHRsIMM/VSHRuIMM nodes in a combine
- because matching i64 constants is difficult -  does not apply for MVE,
as there are not v2i64 shifts. Delaying the creation of the nodes can
allow extra transforms on target independant shl/shr.
2022-05-04 22:12:09 +01:00
Amir Ayupov f8d2d8b587 [BOLT][NFC] Move getInliningInfo out of Inliner class
`getInliningInfo` is useful in other passes that need to check inlining
eligibility for some function. Move the declaration and InliningInfo definition
out of Inliner class. Prepare for subsequent use in ICP.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D124899
2022-05-04 14:08:06 -07:00
Amir Ayupov 2ad1c7540e [BOLT][NFC] Minor cleanup in ICP getCallTargets and canPromoteCallsite
Minor refactoring. NFC.

Reviewed By: rafauler

Differential Revision: https://reviews.llvm.org/D124898
2022-05-04 14:06:53 -07:00
Yitzhak Mandelbaum 9a8d33dbd8 [clang-tidy] Escape diagnostic messages before passing to `diag` in Transformer.
Messages generated by Transformer rules may have `%` in them, which
needs to be escaped before being passed to `diag`, which interprets them
specially (and crashes if they are misused).

Differential Revision: https://reviews.llvm.org/D124952
2022-05-04 20:56:56 +00:00
Ayke van Laethem c1d6dca694
[compiler-rt][AVR] Use correct return value for __ledf2 etc
Previously the default was long, which is 32-bit on AVR. But avr-gcc
expects a smaller value: it reads the return value from r24.

This is actually a regression from https://reviews.llvm.org/D98205.
Before D98205, the return value was an enum (which was 2 bytes in size)
which was compatible with the 1-byte return value that avr-gcc was
expecting. But long is 4 bytes and thus places the significant return
value in a different register.

Differential Revision: https://reviews.llvm.org/D124939
2022-05-04 22:51:39 +02:00
Aaron Ballman b1a55d0895 Fix a crash on targets where __bf16 isn't supported
We'd nondeterministically assert (and later crash) when calculating the size or
alignment of a __bf16 type when the type isn't supported on a target because of
reading uninitialized values. Now we check whether the type is supported first.

Fixes #50171
2022-05-04 16:45:59 -04:00