Commit Graph

152817 Commits

Author SHA1 Message Date
Richard Trieu 0e6e4aa5db Fix up some asserts that are within an if statement. This removes the need
for assert(0 && "text").

llvm-svn: 185396
2013-07-01 23:42:53 +00:00
Jakob Stoklund Olesen 3b4e9ccfe3 Tweak some comments that referred to the old bias computations.
llvm-svn: 185395
2013-07-01 23:36:37 +00:00
Ulrich Weigand f11efe7f48 [PowerPC] Add support for TLS data relocations
This adds support for TLS data relocations and modifiers:
       .quad target@dtpmod
       .quad target@tprel
       .quad target@dtprel
Currently exploited by the asm parser only.

llvm-svn: 185394
2013-07-01 23:33:29 +00:00
Jakob Stoklund Olesen 55daed27b7 Remove floating point computations form SpillPlacement.cpp.
Patch by Benjamin Kramer!

Use the BlockFrequency class instead of floats in the Hopfield network
computations. This rescales the node Bias field from a [-2;2] float
range to two block frequencies BiasN and BiasP pulling in opposite
directions. This construct has a more predictable behavior when block
frequencies saturate.

The per-node scaling factors are no longer necessary, assuming the block
frequencies around a bundle are consistent.

This patch can cause the register allocator to make different spilling
decisions. The differences should be small.

llvm-svn: 185393
2013-07-01 23:19:39 +00:00
Richard Trieu fab01e5cea Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...
llvm-svn: 185392
2013-07-01 23:06:23 +00:00
Howard Hinnant 4a142ec6b0 XFAIL this test on 10.7 and 10.8
llvm-svn: 185391
2013-07-01 22:59:14 +00:00
Ulrich Weigand 704ebd78cb [PowerPC] Fix 32-bit PowerPC TLS relocs
Some TLS relocs were copied incorrectly from ppc64 to ppc32,
and some were missing completely.

llvm-svn: 185390
2013-07-01 22:27:57 +00:00
David Blaikie 1b01ae8648 PR16493: DebugInfo with TLS on PPC crashing due to invalid relocation
Restrict the current TLS support to X86 ELF for now. Test that we don't
produce it on PPC & we can flesh that test case out with the right thing
once someone implements it.

llvm-svn: 185389
2013-07-01 21:45:25 +00:00
Greg Clayton ab70d5dbaa Added SymbolVendorELF to the wrong target (lldb-tool), now it is correctly added to lldb-core.
llvm-svn: 185388
2013-07-01 21:44:02 +00:00
Ulrich Weigand 85c6f7f7a7 [PowerPC] Support all condition register logical instructions
This adds support for all missing condition register logical
instructions and extended mnemonics to the asm parser.

llvm-svn: 185387
2013-07-01 21:40:54 +00:00
Greg Clayton 8918b4b4a2 Fixed Xcode project to include SymbolVendorELF.
llvm-svn: 185386
2013-07-01 21:37:51 +00:00
Chad Rosier 797ee3e3c6 Add a newline.
llvm-svn: 185385
2013-07-01 21:31:10 +00:00
Eli Friedman d02bbeb44e Simplify code in mangler.
llvm-svn: 185384
2013-07-01 21:29:48 +00:00
Manman Ren 74c188f026 Debug Info: clean up usage of Verify.
No functionality change. It should suffice to check the type of a debug info
metadata, instead of calling Verify.

llvm-svn: 185383
2013-07-01 21:02:01 +00:00
Greg Clayton 7fba2634f5 Recognize "decltype(nullptr)" as a valid DW_AT_name for DW_TAG_unspecified_type tags as meaning the C++11 null pointer type.
llvm-svn: 185382
2013-07-01 21:01:52 +00:00
Eli Friedman c48d31c31c Simplify linkage code for static local vars.
The key insight here is that weak linkage for a static local variable
should always mean linkonce_odr, because every file that needs it will
generate a definition.  We don't actually care about the precise linkage
of the parent context.  I feel a bit silly that I didn't realize this before.

llvm-svn: 185381
2013-07-01 20:53:07 +00:00
Bill Schmidt 48fc20a034 Index: test/CodeGen/PowerPC/reloc-align.ll
===================================================================
--- test/CodeGen/PowerPC/reloc-align.ll	(revision 0)
+++ test/CodeGen/PowerPC/reloc-align.ll	(revision 0)
@@ -0,0 +1,34 @@
+; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s
+
+; This test verifies that the peephole optimization of address accesses
+; does not produce a load or store with a relocation that can't be
+; satisfied for a given instruction encoding.  Reduced from a test supplied
+; by Hal Finkel.
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
+
+%struct.S1 = type { [8 x i8] }
+
+@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1
+
+; Function Attrs: nounwind readonly
+define signext i32 @main()  {
+entry:
+  %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*))
+; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l
+  ret i32 %call
+}
+
+; Function Attrs: nounwind readonly
+define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91)  {
+entry:
+  %0 = bitcast %struct.S1* %p_91 to i64*
+  %bf.load = load i64* %0, align 1
+  %bf.shl = shl i64 %bf.load, 26
+  %bf.ashr = ashr i64 %bf.shl, 54
+  %bf.cast = trunc i64 %bf.ashr to i32
+  ret i32 %bf.cast
+}
+
+attributes  = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
Index: lib/Target/PowerPC/PPCAsmPrinter.cpp
===================================================================
--- lib/Target/PowerPC/PPCAsmPrinter.cpp	(revision 185327)
+++ lib/Target/PowerPC/PPCAsmPrinter.cpp	(working copy)
@@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI
       OutStreamer.EmitRawText(StringRef("\tmsync"));
       return;
     }
+    break;
+  case PPC::LD:
+  case PPC::STD:
+  case PPC::LWA: {
+    // Verify alignment is legal, so we don't create relocations
+    // that can't be supported.
+    // FIXME:  This test is currently disabled for Darwin.  The test
+    // suite shows a handful of test cases that fail this check for
+    // Darwin.  Those need to be investigated before this sanity test
+    // can be enabled for those subtargets.
+    if (!Subtarget.isDarwin()) {
+      unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1;
+      const MachineOperand &MO = MI->getOperand(OpNum);
+      if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4)
+        llvm_unreachable("Global must be word-aligned for LD, STD, LWA!");
+    }
+    // Now process the instruction normally.
+    break;
   }
+  }
 
   LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
   OutStreamer.EmitInstruction(TmpInst);
Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp
===================================================================
--- lib/Target/PowerPC/PPCISelDAGToDAG.cpp	(revision 185327)
+++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp	(working copy)
@@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() {
       if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) {
         SDLoc dl(GA);
         const GlobalValue *GV = GA->getGlobal();
+        // We can't perform this optimization for data whose alignment
+        // is insufficient for the instruction encoding.
+        if (GV->getAlignment() < 4 &&
+            (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD ||
+             StorageOpcode == PPC::LWA)) {
+          DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n");
+          continue;
+        }
         ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags);
       } else if (ConstantPoolSDNode *CP =
                  dyn_cast<ConstantPoolSDNode>(ImmOpnd)) {

llvm-svn: 185380
2013-07-01 20:52:27 +00:00
Chad Rosier fa705ee36c [ARMAsmParser] Sort the ARM register lists based on the encoding value, not the
tablegen enum values.  This should be the last fix due to fallout from r185094.

llvm-svn: 185379
2013-07-01 20:49:23 +00:00
Lang Hames 7d99d7977c Make PBQP require/preserve MachineLoopInfo - the spiller requires it.
llvm-svn: 185378
2013-07-01 20:47:47 +00:00
Sean Silva d01eead98c [docs] Amend confusing title
"Writing an LLVM Compiler Backend" can be misinterpreted as meaning
"backend" in the sense of "using LLVM as a backend for your compiler for
your new language". This new name is less ambiguous.

As a bonus, this brings the title in line with the file name.

llvm-svn: 185377
2013-07-01 20:45:12 +00:00
Akira Hatanaka 1af66c9b8a [mips] Reverse the order of source operands of shift and rotate instructions that
have three register operands.

No intended functionality changes.

llvm-svn: 185376
2013-07-01 20:39:53 +00:00
Ulrich Weigand f7152a8596 [PowerPC] Also add "msync" alias
This adds an alias for "msync" (which is used on Book E
systems instead of "sync").

llvm-svn: 185375
2013-07-01 20:39:50 +00:00
Eli Friedman 4747c71427 Fix CMakeLists.txt.
Sorry about that.

llvm-svn: 185374
2013-07-01 20:34:51 +00:00
Akira Hatanaka 263c6af8f3 [mips] Increase the number of floating point control registers available to 32.
Create a dedicated register class for floating point condition code registers and
move FCC0 from register class CCR to the new register class.

llvm-svn: 185373
2013-07-01 20:31:44 +00:00
Eli Friedman 7e346a8127 Fix mangling for block literals.
Blocks, like lambdas, can be written in contexts which are required to be
treated as the same under ODR.  Unlike lambdas, it isn't possible to actually
take the address of a block, so the mangling of the block itself doesn't
matter. However, objects like static variables inside a block do need to
be mangled in a consistent way.

There are basically three components here. One, block literals need a
consistent numbering.  Two, objects/types inside a block literal need
to be mangled using it.  Three, objects/types inside a block literal need
to have their linkage computed correctly.

llvm-svn: 185372
2013-07-01 20:22:57 +00:00
Akira Hatanaka 8b5b1e072f [mips] Fix test case to check that mips64 instructions are generated.
llvm-svn: 185371
2013-07-01 20:18:58 +00:00
Anton Korobeynikov ba8f4c5e29 Really fix the test. Sorry for the breakage...
llvm-svn: 185369
2013-07-01 19:51:36 +00:00
Anton Korobeynikov 0267837076 Fix the test which relies on uncommitted change
llvm-svn: 185368
2013-07-01 19:50:31 +00:00
Cameron Zwarich e35038da94 Fix the build after r185363. Use llvm::next instead of raw next.
llvm-svn: 185367
2013-07-01 19:49:48 +00:00
Michael Sartain a7499c9830 Split symbol support for ELF and Linux.
llvm-svn: 185366
2013-07-01 19:45:50 +00:00
Anton Korobeynikov 82bedb1f3b Add jump tables handling for MSP430.
Patch by Job Noorman!

llvm-svn: 185364
2013-07-01 19:44:44 +00:00
Cameron Zwarich 867bfcd546 Fix PR16508.
When phis get lowered, destination copies are inserted using an iterator that is
determined once for all phis in the block, which BuildMI interprets as a request
to insert an instruction directly before the iterator. In the case of a cyclic
phi, source copies may also be inserted directly before this iterator, which can
cause source copies to be inserted before destination copies. The fix is to keep
an iterator to the last phi and then advance it while lowering each phi in order
to insert destination copies directly after the phis.

llvm-svn: 185363
2013-07-01 19:42:46 +00:00
Anton Korobeynikov ef4129084a Fix MSP430 builtin types.
Patch by Job Noorman!

llvm-svn: 185362
2013-07-01 19:42:40 +00:00
Hal Finkel 25e4a0d418 Don't form PPC CTR loops for over-sized exit counts
Although you can't generate this from C on PPC64, if you have a loop using a
64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had
been cauing the PPCCTRLoops pass to assert.

Thanks to Joerg Sonnenberger for providing a test case!

llvm-svn: 185361
2013-07-01 19:34:59 +00:00
Tim Northover 8625fd8cad AArch64: correct CodeGen of MOVZ/MOVK combinations.
According to the AArch64 ELF specification (4.6.8), it's the
assembler's responsibility to make sure the shift amount is correct in
relocated MOVZ/MOVK instructions.

This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF
(which happened to work out well for JIT tests). This commit should
make us compliant in this area.

llvm-svn: 185360
2013-07-01 19:23:10 +00:00
Matt Beaumont-Gay 8b30c13e12 (1) Add ".test" to test/Other/lit.local.cfg, so llvm-cov.test is actually run.
(2) Rename llvm-cov test inputs so the string "llvm-cov" doesn't get
substituted by lit within the input filenames on the RUN line.
(3) XFAIL llvm-cov.test because it asserts:
include/llvm/ADT/SmallVector.h:140: reference llvm::SmallVectorTemplateCommon<llvm::GCOVBlock *, void>::operator[](unsigned int) [T = llvm::GCOVBlock *]: Assertion `begin() + idx < end()' failed.

llvm-svn: 185358
2013-07-01 18:58:53 +00:00
Jim Ingham d516deb4f2 Formatting cleanup.
llvm-svn: 185357
2013-07-01 18:49:43 +00:00
Tim Northover 7f3d9e1f36 Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")
Turns out I'd misread the architecture reference manual and thought
that was a load/store-store barrier, when it's not.

Thanks for pointing it out Eli!

llvm-svn: 185356
2013-07-01 18:37:33 +00:00
Manman Ren 08016a657c Debug Info: Scope of a DebugLoc should not be null.
No functionality change. Remove handling for the null case.

llvm-svn: 185354
2013-07-01 18:20:30 +00:00
Ulrich Weigand 3a75861b06 [PowerPC] Fix @got references to local symbols
A @got reference must always result in a relocation, so that
the linker has a chance to set up the GOT entry, even if the
symbol happens to be local.

Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces
a relocation to be emitted for GOT references.

llvm-svn: 185353
2013-07-01 18:19:56 +00:00
Marshall Clow 28d8ba5f79 Implement n3656 - make_unique. Thanks to Howard for the review and suggestions.
llvm-svn: 185352
2013-07-01 18:16:03 +00:00
Ulrich Weigand 7a9fcdf6fb [PowerPC] Add "wait" instruction
This adds the "wait" instruction and its extended mnemonics.

llvm-svn: 185350
2013-07-01 17:21:23 +00:00
Ulrich Weigand 98fcc7b6bc [PowerPC] Support "eieio" instruction
This adds support for the "eieio" instruction to
the asm parser.

llvm-svn: 185349
2013-07-01 17:06:26 +00:00
Michael Gottesman fd62bb9d3e Added c++ mode selector to head of SelectionDAGBuilder.h so editors open it in c++ mode instead of c mode.
llvm-svn: 185348
2013-07-01 16:53:41 +00:00
Ulrich Weigand 421843229c [PowerPC] Add some existing instructions to ppc64-encoding-bookII.s
The test case had a couple of FIXMEs where the instruction is in
fact already supported by the back-end.  In some other case, while
the generic form of the instruction is not yet supported, a
specialized form is.  This adds tests for those already supported
instructions / instruction forms.

llvm-svn: 185347
2013-07-01 16:52:55 +00:00
Daniel Jasper ca7bd720eb Fix incorrect token counting introduced by r185319.
This lead to weird formatting.
Before:
DoSomethingWithVector({ {} /* No data */ }, {
  { 1, 2 }
});
After:
DoSomethingWithVector({ {} /* No data */ }, { { 1, 2 } });

llvm-svn: 185346
2013-07-01 16:43:38 +00:00
Alexey Samsonov 4798a08df8 [ASan] try to fix Windows build
llvm-svn: 185345
2013-07-01 16:38:38 +00:00
Ulrich Weigand 797f1a3f5b [PowerPC] Add variants of "sync" instruction
This adds support for the "sync $L" instruction with operand,
and provides aliases for "lwsync" and "ptesync".

llvm-svn: 185344
2013-07-01 16:37:52 +00:00
Marshall Clow d51891063f Implement n3658 - Compile-time integer sequences
llvm-svn: 185343
2013-07-01 16:26:55 +00:00
Alexey Samsonov 9857ca2564 [ASan] Properly disable strict init-order checking when pthread_create is called
llvm-svn: 185342
2013-07-01 16:16:41 +00:00